AVSBus v2.0/1.4.1

An independent clean-room AVSBus controller Bus Functional Model — unlike the I2C/SMBus/PMBus family’s open-drain, multi-drop buses vip-smbus/vip-pmbus build on, AVSBus is point-to-point (exactly one controller, one target, no shared wire, no address arbitration), push-pull (no _oe, no bus contention to resolve), and the CONTROLLER ALONE drives the link clock — the target never stretches it. So this BFM’s bit-serial primitives are new, not extended from i2c_master_bfm.sv‘s open-drain bit/byte tasks the way smbus_master_bfm.sv/pmbus_master_bfm.sv are — there is nothing shaped like this bus anywhere else in the OSS VIP set to build on. Its timing (frame-assert settle margin before the first avsclk toggle, avsclk toggle rate relative to the design’s own clk, request-bit drive-then-clock order, response-bit sample point, frame-deassert timing) is a direct translation of the paired avsbus_target IP’s own proven-correct native C++ interop testbench (tb_avsbus_target_interop.cpp), not re-derived from scratch — this DUT’s synchronizer chains on avsclk_i/avsframe_n_i/avsdata_i make timing margin genuinely easy to get subtly wrong, so mirroring a working reference is the lower-risk path. WRITE/READ tasks drive a well-formed 21-bit request (RW+PSN+ADDR+DATA+PARITY) and capture the 10-bit response (DATA+STATUS+PARITY); WRITE_BAD_PARITY deliberately corrupts the request’s own parity bit; ABORT deasserts the frame strobe partway through a transaction; HOLD_FRAME asserts the frame strobe without ever toggling the link clock, for the bus-stuck-timeout scenario. A passive protocol checker independently reconstructs the 21-bit request + 10-bit response off the DUT’s real avsframe_n_i/avsclk_i/avsdata_i/avsdata_o pins with its own from-scratch bit-serial decode (sharing no code or instance with the master BFM) — critically, it runs its OWN 2-3 stage synchronizer + edge detect on avsclk_i/avsframe_n_i (the same generic technique the DUT itself applies, not copied logic) so its notion of when the DUT has reacted to an edge lands on the same cycle the DUT’s internal logic does, correctly timing its capture of the DUT-driven response bits. It independently recomputes both parity fields, independently validates the ADDR-legality rule (0x00/0x01/0x02 only), cross-checks a valid write’s response DATA against the just-captured request DATA (a purely protocol-level echo check needing no DUT register-state knowledge), and confirms every completed (non-aborted) frame spans exactly 31 avsclk cycles. This second-source effort ran clean against avsbus_target: 0 checker violations across a VSET write + VOUT_RB read-back round trip on two PSN domains (confirming domain isolation), a write to the read-only STATUS address (protocol-valid, no register side effect), an invalid ADDR and a request-parity-corrupted frame (both err_code 3), a VSET write above THRESH_MAX (confirmed LIVE, non-sticky domain- and CSR-level fault reporting that self-clears on the next read once VSET drops back below threshold, no command needed), an early frame-abort (confirmed no register side effect and clean recovery), and a bus-stuck whole-transaction timeout (err_code 4, confirmed clean recovery), with no false ASIL-B self-check trip (err_code 1/2/9) at any point. Explicitly out of scope: this catalog’s own clean-room bit-mapping (field widths/positions/parity scheme) needs reconciliation against the licensed AMD AVSBus specification before real silicon integration — inherited directly from avsbus_target‘s own v1 scope note, not a limitation of this VIP; no real closed-loop DVFS droop-response analog timing (the paired DUT’s VSET/VOUT_RB registers are a documented protocol-framing model, not a real regulation loop); and no multi-domain/multi-target addressing beyond the 8 PSN slots avsbus_target itself implements.

Key Features

• Independent AVSBus controller BFM: from-scratch bit-serial primitives (new, not extended from the I2C-family open-drain tasks) timed off the paired DUT’s own proven C++ interop reference — WRITE/READ, a deliberate bad-request-parity negative-test variant, an early-frame-abort task, and a raw frame-hold task for the bus-stuck-timeout scenario
• Passive protocol checker: from-scratch 21-bit-request/10-bit-response bit-serial decode off the DUT’s real avsframe_n_i/avsclk_i/avsdata_i/avsdata_o pins (no code/instance sharing with the master BFM), running its OWN synchronizer chain to correctly time its capture of the DUT-driven response bits, independently recomputing both parity fields, validating ADDR legality, cross-checking a valid write’s response-DATA echo, and confirming exact 31-cycle frame length on every completed frame
• Directed scenarios cross-checked against the checker’s independent decode: a VSET write + VOUT_RB read-back round trip on two domains (confirming domain isolation), a write to the read-only STATUS address (protocol-valid, no side effect), an invalid ADDR and a request-parity-corrupted frame (both err_code 3), a VSET write above THRESH_MAX (live, non-sticky domain/CSR fault reporting), an early frame-abort (no side effect, clean recovery), and a bus-stuck whole-transaction timeout (err_code 4, clean recovery) — 0 checker violations, no false err_code 1/2/9
• Honestly scoped: this catalog’s own clean-room bit-mapping needs reconciliation against the licensed AMD AVSBus specification (inherited from the paired DUT’s own v1 scope, not a VIP limitation); no real closed-loop DVFS droop-response analog timing; no multi-domain/multi-target addressing beyond the DUT’s own 8 PSN slots

Standards & Compliance

Adaptive Voltage Scaling Bus (AVSBus) Specification v2.0/1.4.1

Pairs With

Built to lean against these catalog IPs during integration:

• avsbus_target