← All Verification IPChiplet / Die-to-Die
BoW (Bunch of Wires)
Low-cost parallel die-to-die PHY verification for the open Bunch-of-Wires interface — an alternative to UCIe for organic-substrate chiplet links.
plannedGroup Chiplet / Die-to-DieStandard OCP ODSA Bunch of Wires (BoW) die-to-die PHY
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
Low-cost parallel die-to-die PHY verification for the open Bunch-of-Wires interface — an alternative to UCIe for organic-substrate chiplet links.
Key Features
- Parallel single-ended die-to-die signaling verification
- Source-synchronous clock-forwarding and lane-to-lane skew scenarios
Standards & Compliance
OCP ODSA Bunch of Wires (BoW) die-to-die PHY
Interested in the BoW (Bunch of Wires) VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
circuit-design.space · +1-971-357-1400 · sales@circuit-design.space