← All Verification IPAMBA / On-Chip Bus
CXS c/d/Lite
The remaining CXS layer variants (C/D/Lite) complementing the CXS-A/B VIP above, for lighter-weight or alternate chip-to-chip CHI extension configurations.
plannedGroup AMBA / On-Chip BusStandard Arm CHI-CXS (Chip-to-Chip Extension) — CXS-C/D/Lite layers
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
The remaining CXS layer variants (C/D/Lite) complementing the CXS-A/B VIP above, for lighter-weight or alternate chip-to-chip CHI extension configurations.
Key Features
- CXS-C/D layer flit-transport framing verification
- CXS-Lite reduced-overhead mode scenarios
Standards & Compliance
Arm CHI-CXS (Chip-to-Chip Extension) — CXS-C/D/Lite layers
Interested in the CXS c/d/Lite VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
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