← All Verification IPMemory
DDR5/4/3
Multi-generation DDR SDRAM controller/PHY-side verification — command/address decode, on-die termination, and refresh/RAS-timing sweep across three DDR generations.
plannedGroup MemoryStandard JEDEC DDR5 (JESD79-5), DDR4 (JESD79-4), DDR3 (JESD79-3)
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
Multi-generation DDR SDRAM controller/PHY-side verification — command/address decode, on-die termination, and refresh/RAS-timing sweep across three DDR generations.
Key Features
- Command/address decode and on-die-termination (ODT) sequencing per generation
- Refresh, RAS-timing (tRCD/tRP/tRAS), and bank-group interleave scenarios
- DDR5 decision-feedback equalization (DFE) and same-bank refresh (DDR5-specific) coverage
Standards & Compliance
JEDEC DDR5 (JESD79-5), DDR4 (JESD79-4), DDR3 (JESD79-3)
Interested in the DDR5/4/3 VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
circuit-design.space · +1-971-357-1400 · sales@circuit-design.space