Available now — real, tested verification collateral, not a roadmap placeholder.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
An independent clean-room DisplayPort “sink” BFM — written from the public DP 1.4 AUX-channel and main-link framing spec, not from the catalog’s own dp_link FSMs — decodes the DUT’s real Manchester-encoded native-AUX requests (native AUX only; I2C-over-AUX is not implemented by this DUT) off its digital aux_out_o/aux_oe_o pins and replies with ACK/NACK + DPCD data from its own in-memory model, timed to land inside the DUT’s own sampling window. A passive main-link checker independently decodes BS/TU_HDR/PIXEL/BE byte framing off serdes_data_o (a real 8b/10b/electrical D-PHY-class SerDes layer is out of scope, matching dp_link‘s own “digital-only, connects to an external SerDes” scope) and independently recomputes the LFSR-16 scrambler. dp_link‘s own link-establishment is a simplified Technology-Preview model (CTRL.EN directly asserts LINK_UP; there is no real clock-recovery/channel-equalization training state machine to verify) — scoped honestly to what the DUT actually implements. This second-source effort surfaced and fixed (2026-07-09) three real RTL findings: (1) the AUX request’s transmitted CMD field read a stale, pre-update copy of the write/read direction flag, so the first AUX transaction after reset (and any transaction whose direction differed from the one before it) transmitted the wrong command — fixed by using the fresh trigger signal directly; (2) the main-link TU header unconditionally declared 32 valid symbols even when a line’s final transfer unit was shorter — fixed with a new wait state that holds until it is actually known whether a full transfer unit is achievable or the line has genuinely ended, so the declared length always matches what is actually sent; (3) the 256-byte pixel FIFO’s fullness check only guarded a 1-byte margin against a 3-byte-per-cycle burst write, letting a sustained pixel burst wrap around and corrupt not-yet-read data — fixed by guarding the full 3-byte burst. None of the three ever tripped the DUT’s own ASIL-B safety monitor; all three are verified against the DUT’s native regression and formal BMC+cover proofs, plus this VIP’s own tests with stash/revert sanity checks proving each fix independently.
VESA DisplayPort 2.0 / 1.4
Built to lean against these catalog IPs during integration:
Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space