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DisplayPort 2.1

An independent clean-room DisplayPort 2.1 UHBR 128b/132b link-layer VIP: a source BFM, a separately written sink, and a passive link-layer checker (dp21/, make dp21_oss, 11/11 checks).

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shippingGroup DisplayStandard VESA DisplayPort 2.1

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model
An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.
Passive protocol checker
A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.
Self-checking interop testbench
A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent clean-room DisplayPort 2.1 UHBR 128b/132b link-layer VIP: a source BFM, a separately written sink, and a passive link-layer checker (“dp21/, make dp21_oss, 11/11 checks). A SIBLING of vip-dp20, not an extension of it — UHBR replaces 8b/10b with 132-bit block coding, so the DP 1.4 Transfer-Unit framing that VIP checks is not what is on the wire. The source emits 132-bit blocks (4-bit sync header + 128-bit payload) with a scrambler that runs CONTINUOUSLY across blocks and is reset only by an SR block; the sink maintains its OWN descrambler, seeded only from an SR it observes on the wire. The checker is passive: sync-header legality, SR cadence, FEC grouping, and no payload before the first reset. SCOPE, stated rather than implied: LINK TRAINING and MST are NOT modelled — this catalog has no UHBR DUT, and dp_link’s own link-up is a simplified Technology-Preview model with no clock-recovery/equalisation state machine to be a second source to. The block-type codewords are public-spec constants to re-check against VESA before any conformance claim; the checker’s rules are structural and do not depend on them. The VIP’s most useful result is a NEGATIVE one: a source that re-seeds its scrambler per block emits structurally PERFECT blocks that no passive rule can catch — a heuristic written to catch it was removed rather than left in looking useful, and T7 asserts that every structural rule stays SILENT while the independent sink stops recovering the payload. That is the argument for shipping a second source instead of grading a stream against the model that produced it.

Key Features

Standards & Compliance

VESA DisplayPort 2.1

Pairs With

Built to lean against these catalog IPs during integration:

Interested in the DisplayPort 2.1 VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space