Display

eDP 2.0

Embedded DisplayPort verification for internal panel links — the eDP-specific power-sequencing and panel-self-refresh extensions on top of the base DisplayPort protocol.

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plannedGroup DisplayStandard VESA Embedded DisplayPort (eDP) 2.0

Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What is scoped

Scoped, not yet built

This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.

Ask if you need it sooner

Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.

Same shape when it lands

Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.

Embedded DisplayPort verification for internal panel links — the eDP-specific power-sequencing and panel-self-refresh extensions on top of the base DisplayPort protocol.

Key Features

Panel power-sequencing (backlight/panel-enable timing) verification
Panel Self-Refresh (PSR) entry/exit scenarios

Standards & Compliance

VESA Embedded DisplayPort (eDP) 2.0

Pairs With

Built to lean against these catalog IPs during integration:

dp_link

Interested in the eDP 2.0 VIP?

This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space