LPDDR5 / 5X

An independent clean-room “PHY + DRAM” Bus Functional Model — written from the public CA[6:0] serial-frame mapping the catalog’s own lpddr5_pkg.sv documents as a clean-room invention pending reconciliation against the licensed JESD209-5 CA truth table, and from the real DFI 5.x training/init handshake signal names, not from lpddr5_ctrl‘s own internal FSMs — decodes the DUT’s real CA[6:0]/dfi_cs command frames off its digital DFI pins with a fresh, from-scratch decode function (never calling the DUT’s own lpddr5_pkg::ca_enc/ca_len), drives the init/mode-register-write/training bring-up handshake through mechanically, and models ACT/RD/WR/PRE/PREA/REF against a simple internal per-bank-open-row memory for a byte-exact AXI4 host round-trip. A passive checker independently re-decodes the same CA[6:0]/dfi_cs pins (its own separate frame-length table and reassembly FSM, sharing no code or instance with the BFM’s decoder) and cross-checks the declared frame length against dfi_cs‘s assertion span, catching any frame-overlap/malformed-frame condition. In scope this wave: the documented CA-bus bit mapping, the DUT’s own bring-up FSM order (E_INIT -> E_MRWINIT -> E_TRAIN -> E_IDLE, driven through mechanically, not deeply timing-verified), ACT/RD/WR/PRE/PREA/REF command semantics, and directed byte-exact AXI4 write-then-read-back round trips exercising the DUT’s own open-page engine (ACT on a closed bank, PRE-then-ACT on a row change within the same bank, independent per-bank open-row state) — cross-checked against the passive checker’s independently-decoded op sequence. Explicitly out of scope this wave: mode-register CONTENT (MRW frames are counted/consumed, not interpreted), per-bank refresh/RFM/RAA, link-ECC, deep training-sequence correctness, low-power, DVFS, and out-of-order scheduling — these are separate DFI sub-interfaces this wave neither drives nor verifies, with their DUT-facing inputs tied off harmlessly. This second-source effort ran clean against the DUT with no RTL findings to report this wave: 0 checker violations, byte-exact round trips at multiple (bank, row, col) combinations, and the checker’s independently-decoded CA sequence exactly matching what the AXI-level test intended, including the PRE-then-ACT sequence a same-bank row change must produce.

Key Features

• Independent “PHY + DRAM” BFM: from-scratch CA[6:0]/dfi_cs frame decode (own frame-length table, never the DUT’s own lpddr5_pkg::ca_enc/ca_len), mechanical init/MRW/training bring-up walkthrough, ACT/RD/WR/PRE/PREA/REF command modeling against a simple per-bank open-row memory
• Passive CA-frame checker: independent frame reassembly (separate code/instance from the BFM), declared-length-vs-dfi_cs-span cross-check (frame-overlap/malformed-frame detection), a decoded-op queue the TB cross-checks against its own intended AXI-level command sequence
• Byte-exact directed AXI4 write/read-back round trips across ACT-on-closed-bank, PRE-then-ACT-on-row-change, and independent-per-bank-open-row scenarios
• Clean-room: CA-bus decode written from the DUT’s own public header-documented bit mapping, not from its internal FSM bodies — never reads the DUT’s decoded-command debug bus (dfi_cmd/dfi_bank/dfi_row/dfi_col)

Standards & Compliance

JEDEC LPDDR5 / LPDDR5X (JESD209-5)

Pairs With

Built to lean against these catalog IPs during integration:

• lpddr5_ctrl