Available now — real, tested verification collateral, not a roadmap placeholder.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
A clean-room PCI Express agent pair — Root Complex and Endpoint — written from the public PCI-SIG base specification and connected by a genuine serial wire, one bit per clock, not a pre-decoded symbol bus. Four layers ship as separate, separately readable modules: a physical coding sublayer with the full 8b/10b transmission code (both sub-block tables, running-disparity chaining, the D.x.A7 alternate encoding, comma alignment, invalid-code and disparity-error detection) and Gen3 128b/130b block encoding (2-bit sync headers, EIEOS block alignment, the specification’s scrambling polynomial); an LTSSM that really walks Detect → Polling → Configuration → L0 exchanging TS1/TS2 ordered sets and negotiating link and lane numbers; a data link layer with 12-bit sequence numbers, LCRC-32, DLLP CRC-16, and working Ack/Nak with replay from a real replay buffer; and a transaction layer with Memory and Configuration reads and writes, tag-matched completions, Unsupported Request and Completer Abort. The speed change to Gen3 is a real Recovery walk — TS1/TS2 with the speed-change bit, an announced Electrical Idle via EIOS, then block re-alignment on EIEOS and data-stream entry on SDS — not a mode flag. A passive protocol checker watches each direction of the raw wire with its own independent 8b/10b decoder (written in the decode direction, not as the reverse map of the encoder) and its own bit-at-a-time CRC implementations, and detects the link speed from the wire rather than being told it.
The wire encodings are the normative ones. Every field that goes on the link is built to the PCI-SIG base specification: the 8b/10b transmission code, the TS1/TS2 ordered sets, the Gen3 Framing Tokens (STP with its 11-bit TLP Length, 12-bit Sequence Number, 4-bit Frame CRC and Frame Parity; SDP = F0h ACh; EDB; IDL), and both CRCs — LCRC-32 from polynomial 04C11DB7h and the DLLP CRC-16 from polynomial 100Bh, each seeded all-ones, complemented, and placed on the wire with the bits reversed within each byte exactly as the specification’s bit-mapping tables require. The testbench pins these against external values rather than against itself: published check values for the CRC engines, and the specification’s own published EDS Token bits as a check vector for the Frame CRC and Frame Parity equations.
It has been trained against a third-party commercial PCIe controller. There is no PCIe RTL in this catalog to pair with, so interop was established out-of-tree instead: the BFM drives a commercial controller’s RTL over a 32-bit PIPE interface through a PHY-side adapter, and that controller’s own LTSSM state output walks the full sequence — Detect → Polling.Active → Polling.Configuration → Configuration.Linkwidth/Lanenum → Configuration.Idle → L0, and stays in L0. TLPs are then exchanged with it: the controller acknowledges our packets — accepting our STP framing, sequence numbers and LCRC-32 byte order — and a deliberately corrupted LCRC draws a real Nak, after which our replay buffer retransmits, the controller acknowledges the replay, and both ends walk Recovery back to L0. The harness lives in tb/validation/ (the controller RTL is proprietary and is not in this repository; see the README there). That exercise found five defects the BFM-pair self-check structurally could not: a Polling exit with no minimum-transmit condition, training sets that were not back-to-back, flow-control initialisation covering only the Posted category, missing periodic SKP Ordered Sets, and no Recovery re-entry at all. All five are fixed — they are the difference between two copies of the same assumptions agreeing with each other and a real implementation accepting the link.
The Gen3 speed change and Link Equalization run against it in full. With its Target Link Speed programmed over the controller’s local-management APB, the controller recognises our speed_change request, reaches Recovery.Speed and drives PIPE_RATE=010, walks the whole Recovery.Equalization phase sequence (Phase 0 preset in RcvrCfg, then the Phase 1→3 EC walk carried in the EC field of our 8 GT/s TS1), and comes up in L0 at 8 GT/s on a block-aligned, error-free 128b/130b data stream in both directions — and remains in L0 to the end of the run. Reaching it settled two deep points: the Gen3 scrambler is the specification’s Galois LFSR, not a Fibonacci realisation of the same polynomial (the two produce different scrambled streams, and only the Galois form descrambles on a real partner) — now verified bit-for-bit against the controller’s own scrambler RTL, Lane-0 seed 1DBFBCh; and the 32-bit PIPE PCLK must scale with the data rate (62.5 MHz at Gen1, 250 MHz at Gen3) or the controller’s Gen3 elastic buffer starves and its loss-of-block-alignment check drops it out of L0 — a harness clock-rate detail, since the shippable VIP is bit-serial and rate-agnostic. Across all three stages the interop found nine defects the self-check structurally could not, including the Fibonacci-vs-Galois Gen3 scrambler and a speed_change request advertised on the wrong Data Rate Identifier bit — all fixed.
Scope, stated plainly. What is demonstrated against a third-party controller is Gen1 link training and sustained L0, the full 8 GT/s speed change plus Link Equalization, and sustained Gen3 (8 GT/s) L0, together with data-link-layer TLP exchange including the Nak/replay/Recovery error path. Transaction-layer interop is NOT demonstrated: that controller emits no TLPs of its own under this harness (its application side is not brought up here), so no completion has been received from it. None of this is a compliance claim. Also out of scope: x1 only (no multi-lane striping, deskew or lane reversal), reduced ordered-set counts on the LTSSM state transitions, no L0s/L1/L2 power states, no ECRC, no MSI/INTx/message TLPs, no IO space, and flow-control credits are initialised and advertised but not accounted.
PCI-SIG PCI Express Base Specification, Gen 3 (8 GT/s) / Gen 2 (5 GT/s)
Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space