← All Verification IPPCIe / CXL
PCIe Gen 3/2
Earlier-generation PCIe PHY/link-layer verification, sibling to the Gen 5/4 and Gen 6/7 VIPs for legacy-platform coverage.
plannedGroup PCIe / CXLStandard PCI-SIG PCI Express Base Specification, Gen 3 (8 GT/s) / Gen 2 (5 GT/s)
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
Earlier-generation PCIe PHY/link-layer verification, sibling to the Gen 5/4 and Gen 6/7 VIPs for legacy-platform coverage.
Key Features
- 128b/130b (Gen3) and 8b/10b (Gen2) encoding verification
- Link-training (LTSSM) and TLP/DLLP framing scenarios
Standards & Compliance
PCI-SIG PCI Express Base Specification, Gen 3 (8 GT/s) / Gen 2 (5 GT/s)
Interested in the PCIe Gen 3/2 VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
circuit-design.space · +1-971-357-1400 · sales@circuit-design.space