Timers & Peripherals

PIT (Programmable Interval Timer)

An independent APB4 timer configuration master, written clean-room from the PIT register map — not derived from our own timer RTL — so it functions as a true second source.

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shippingGroup Timers & PeripheralsStandard Generic PIT verification (no fixed external spec)

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent APB4 timer configuration master, written clean-room from the PIT register map — not derived from our own timer RTL — so it functions as a true second source. Ships with a passive period checker that measures the elapsed-cycle gap between consecutive timer_irq rising edges against the period the TB itself configured, self-re-arming for auto-reload mode, and a self-checking interop TB proving the overflow cadence (polled and cleared across several periods, since timer_irq is a level signal) plus PWM sanity against the catalog’s timer. Covers auto-reload-mode period timing today — one-shot mode, count-down direction, and DMA-trigger-pulse timing are a documented roadmap item, not yet built.

Key Features

Independent APB4 config master: WR/RD task API (PSC/ARR/CR)
Passive period checker: measures the timer_irq inter-edge gap against the TB-configured period, never reading DUT-internal state
Self-checking interop TB against the catalog’s timer: auto-reload overflow cadence (poll-and-clear), PWM sanity — all pass
Scope today is auto-reload-mode period timing; one-shot mode, count-down direction, and DMA-trigger timing are roadmap, not yet built

Standards & Compliance

Generic PIT verification (no fixed external spec)

Pairs With

Built to lean against these catalog IPs during integration:

timer

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Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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