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RI5CY
Instruction-level and bus-level verification for the RI5CY RISC-V core family (the PULP predecessor to CV32E40P) — an OBI-bus core the catalog’s own OBI VIP can already drive at the bus…
plannedGroup Cores / On-Chip Infra / MiscStandard PULP-Platform RI5CY (RISC-V RV32IMC) core conventions
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
Instruction-level and bus-level verification for the RI5CY RISC-V core family (the PULP predecessor to CV32E40P) — an OBI-bus core the catalog’s own OBI VIP can already drive at the bus level.
Key Features
- RV32IMC instruction-stream generation and self-checking scoreboard
- OBI bus-level verification, reusing the catalog’s own OBI VIP at the interface boundary
Standards & Compliance
PULP-Platform RI5CY (RISC-V RV32IMC) core conventions
Interested in the RI5CY VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
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