← All Verification IP
Timers & Peripherals

RTC

An independent APB4 RTC configuration master, written clean-room from the RTC register map — not derived from our own rtc RTL — so it functions as a true second source.

Request this VIP →Browse all VIP
shippingGroup Timers & PeripheralsStandard Generic calendar/alarm RTC verification (no fixed external spec)

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model
An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.
Passive protocol checker
A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.
Self-checking interop testbench
A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent APB4 RTC configuration master, written clean-room from the RTC register map — not derived from our own rtc RTL — so it functions as a true second source. Ships with a passive alarm-timing checker that predicts the rtc_irq alarm-match edge from an H:M:S delta the TB itself computed, and a self-checking interop TB proving alarm timing plus the RTL’s documented Feb-fixed-28-days calendar-rollover quirk (cascading through hour/day/month, verified by direct register readback — there’s no dedicated output pin for calendar state) against the catalog’s rtc. Real calendar-logic scope, not a register-toggle smoke test — leap-year handling isn’t covered since the RTL itself doesn’t implement it (fixed 28-day February by design).

Key Features

Standards & Compliance

Generic calendar/alarm RTC verification (no fixed external spec)

Pairs With

Built to lean against these catalog IPs during integration:

Interested in the RTC VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

Talk to us →See related VIP

Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space