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Serial & Control Bus

SMBus v3.3.1/3.2

An independent clean-room SMBus master Bus Functional Model — extended from the catalog’s own i2c_master_bfm.sv open-drain bit/byte primitives (this repo’s own OSS VIP code…

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shippingGroup Serial & Control BusStandard System Management Bus (SMBus) Specification v3.3.1/3.2

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model
An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.
Passive protocol checker
A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.
Self-checking interop testbench
A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent clean-room SMBus master Bus Functional Model — extended from the catalog’s own i2c_master_bfm.sv open-drain bit/byte primitives (this repo’s own OSS VIP code, not a DUT-internal artifact, so reuse between two VIPs carries no clean-room concern) with the SMBus-specific behavior plain I2C does not have: clock-stretch-aware SCL release (poll the wire after releasing, honouring an arbitrary-length slave stretch), the catalog smbus_slave‘s own per-data-byte PEC (CRC-8) framing, and an Alert Response Address (ARA) task — drives the DUT’s real open-drain scl_i/scl_oe/sda_i/sda_oe/smbalert_n_oe pins directly, not a debug shortcut. A passive protocol checker independently reconstructs the byte stream off those same five pins with its own from-scratch edge-detect/shift-register decode (sharing no code or instance with the master BFM) and its own bit-serial CRC-8 re-derivation, cross-checking address/data/PEC framing, ACK/NACK correctness (including an asymmetric rule that only unconditionally flags a DUT-transmitted PEC mismatch on a READ, since a WRITE’s PEC content is test-chosen and a directed negative test deliberately sends a wrong one — what actually matters there is that the DUT’s NACK response is independently confirmed correct), an ARA/SMBALERT# cross-check, and drive-direction consistency against the DUT’s own scl_oe/sda_oe. The clock-stretch scenario proves the wait was real by direct instrumentation, not inference: the master BFM counts every clk cycle its own poll-before-rise loop spends genuinely blocked, and a baseline (STRETCH_EN=0) run is diffed against a stretched run to show zero blocked cycles vs. a nonzero, directly-attributed count. This second-source effort ran clean against smbus_slave: 0 checker violations across plain write/read, wrong-address NACK, PEC-enabled write (correct and deliberately-wrong PEC), PEC-enabled read, clock stretch, ARA, and a clock-low bus-timeout scenario, with no false ASIL-B self-check trip (err_code 1/2/9) at any point. Explicitly out of scope: Host Notify, full ARP (Address Resolution Protocol) / dynamic addressing, multi-master bus arbitration, and SMBus 3.0 vendor extensions — none of these are implemented by the paired smbus_slave DUT this wave. Also explicitly not a VIP limitation but a documented DUT scope choice this VIP verifies AS SPECIFIED: PEC here is computed and checked PER DATA BYTE (address+R/W byte + that one data byte, re-based fresh each byte), not as a single CRC-8 covering an entire multi-byte block the way strict SMBus PEC framing does — smbus_slave.sv‘s own header documents this as a deliberate v1 scope deviation, and this VIP’s checker independently verifies exactly that per-byte scheme, not the block form.

Key Features

Standards & Compliance

System Management Bus (SMBus) Specification v3.3.1/3.2

Pairs With

Built to lean against these catalog IPs during integration:

Interested in the SMBus v3.3.1/3.2 VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space