PCIe / CXL

SR-IOV

PCIe device-virtualization verification — Physical/Virtual Function (PF/VF) configuration-space and VF-to-PF mailbox scenarios.

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plannedGroup PCIe / CXLStandard PCI-SIG Single Root I/O Virtualization and Sharing (SR-IOV) Specification

Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What is scoped

Scoped, not yet built

This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.

Ask if you need it sooner

Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.

Same shape when it lands

Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.

PCIe device-virtualization verification — Physical/Virtual Function (PF/VF) configuration-space and VF-to-PF mailbox scenarios.

Key Features

PF/VF configuration-space (SR-IOV extended capability) verification
VF enable/disable and VF-to-PF mailbox-message scenarios

Standards & Compliance

PCI-SIG Single Root I/O Virtualization and Sharing (SR-IOV) Specification

Interested in the SR-IOV VIP?

This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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