Available now — real, tested verification collateral, not a roadmap placeholder.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
An independent clean-room USB Power Delivery 3.1 protocol-layer VIP: a Source BFM that holds its own capability list and drives a modelled VBUS rail, a separately written Sink BFM that keeps ITS OWN copy of that list and lives with whatever voltage arrives, and a passive protocol checker (“usbpd/, make usbpd_oss, 25/25 checks). Seven rules — GoodCRC echo and presence, MessageID progression across Soft_Reset, Object Position in range (including the reserved position 0), requested current within the selected PDO, PS_RDY only after Accept, and Request object count — each with a test that fires it. SCOPE: the protocol layer and the policy engine above it. The BMC-encoded CC wire (biphase mark coding, 4b5b, the packet CRC) is the PD PHY and is NOT modelled; messages are typed transactions. Chunked Extended messages, PPS/APDO regulation, EPR and cable-plug SOP’/SOP” discovery are out of scope and the package header says so rather than listing them. This is the one VIP in the catalog whose failure mode is physical: a mis-negotiated contract puts real voltage on a real pin, and its sharpest test is a NEGATIVE one. T9 re-advertises the capability list while the sink’s policy decision is already taken: Object Position 2 was 9 V when the sink chose it and is 20 V when the source honours it. Every field is legal — position in range, current within the PDO, IDs correct, GoodCRCs present — so the passive checker is blind by construction, and a 9 V-rated sink takes 20 V. The wire carries an INDEX into a list and no record of which version the sink was reading; the protection is a policy-engine obligation no monitor can enforce.
USB-IF USB Power Delivery Specification v3.1 — protocol layer
Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space