xSPI (expanded SPI)

An independent QSPI flash DEVICE model, written clean-room from the generic de facto fast-read quad-I/O flash-vendor command convention (opcode byte, address bytes, dummy cycles, then a quad-I/O data burst) — not derived from our own qspi_xip RTL — so it functions as a true second source on the flash side of the link. Ships with a passive protocol checker enforcing SCK-idle-while-deselected, CS-only-changes-while-SCK-low, and quad-I/O tri-state/bus-contention legality during the data-in phase, plus a self-checking interop TB proving an end-to-end OBI fetch through the catalog’s qspi_xip XIP controller returns exactly the flash model’s WRITE_MEM-programmed data. Covers quad-I/O (x4) fast-read with 3-byte (24-bit) addressing only, SDR only — 4-byte addressing, x1/x2/x8 modes, DDR, SFDP discovery, and dynamic protocol-mode switching are a documented roadmap item, not yet built.

Key Features

• Independent QSPI flash device model: quad-I/O (x4) fast-read command decode (opcode + 24-bit address + configurable dummy cycles) with a WRITE_MEM-programmable memory array
• Passive protocol checker: SCK-idle-while-deselected, CS-only-changes-while-SCK-low, quad-I/O tri-state/bus-contention legality on the data-in phase
• Self-checking interop TB against the catalog’s qspi_xip: independent APB4 config BFM programs the controller, OBI-side fetches confirm end-to-end data correctness across distinct-line + line-buffer-hit scenarios
• Scope today is quad-I/O (x4) fast-read, 3-byte addressing, SDR only; x1/x2/x8 modes, 4-byte addressing, DDR, SFDP discovery, and dynamic protocol switching are roadmap, not yet built

Standards & Compliance

JEDEC JESD251A (xSPI) + JESD216D-01 (SFDP)

Pairs With

Built to lean against these catalog IPs during integration:

• qspi_xip