Available now — real, tested verification collateral, not a roadmap placeholder.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
An independent ARINC 429 line-level transceiver, written clean-room from the public ARINC 429 word-format specification — not derived from our own arinc429 RTL — so it functions as a true second source. Ships with a passive protocol checker that independently recomputes ODD parity over each 32-bit word and verifies the bit-period grid (both low-speed 12.5 kbit/s and high-speed 100 kbit/s) on the wire, plus a self-checking interop TB proving both directions (RX into the catalog arinc429, TX out of it) at both speeds against the real APB4 register interface, including the label-based accept-list filter. Covers the core word-level protocol (LABEL/SDI/DATA/SSM framing, odd parity, dual bit-rate timing, label filtering) — BPRZ line-level (analog) encoding and multi-drop bus contention are out of scope, matching the DUT’s own digital-model boundary.
SEND_WORD/RECV_WORD task API + a SEND_WORD_BAD_PARITY error-injection primitive, both LP_DIV (12.5 kbit/s) and HP_DIV (100 kbit/s) bit-period coveragearinc429: RX path, TX path, and the label-based accept-list filter (accept/reject) — all pass at both speedsARINC 429 (Mark 33 Digital Information Transfer System)
Built to lean against these catalog IPs during integration:
Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
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