CSI-2 v4.0.1

An independent clean-room “camera” BFM — written from the public CSI-2 packet spec, not from the catalog’s own csi2_rx FSM — drives the real DUT over its byte-parallel digital D-PHY interface (SoT/valid/byte-clock; the electrical D-PHY layer itself is out of scope, matching csi2_rx‘s own “Digital-only, connects to an external D-PHY hard macro” scope) with independently recomputed Hamming(6,1) header ECC and CRC-16/CCITT payload checks. A passive checker watches the same wire and re-validates both independently. Covers short-packet sync events (Frame/Line Start/End), long-packet RAW8 payload framing, VC/DT routing and filtering, and directed single-bit (corrected), double-bit (discarded), and payload-CRC error injections. This second-source effort surfaced a real RTL finding, fixed 2026-07-09: the DUT’s single-bit ECC correction targeted the wrong bit (a Hamming codeword-position vs. raw-data-index mixup), so a “corrected” packet was silently mis-decoded into a different, wrong packet — fixed by mapping the codeword position to the correct data index; this VIP’s own T3 now proves the fix recovers the exact original header.

Key Features

• Independent camera BFM: clean-room Hamming(6,1) header ECC + CRC-16/CCITT payload encode, with directed single-bit/double-bit ECC and bad-CRC injection knobs
• Passive protocol checker independently re-decodes every packet off the real shared wire and cross-checks against the DUT’s own APB-exposed status/INTR/ERR_CNT registers
• Short-packet sync-event framing (Frame/Line Start/End), long-packet RAW8 payload framing, VC-enable/DT-filter routing coverage
• A real ECC single-bit-correction bug was found and fixed (wrong-bit correction, now recovers the exact original header) — see the write-up above

Standards & Compliance

MIPI CSI-2 v4.0.1

Pairs With

Built to lean against these catalog IPs during integration:

• csi2_rx