Timers & Peripherals

GPIO

An independent GPIO pin driver, written clean-room against the pad-level contract — not derived from our own gpio RTL — so it functions as a true second source.

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shippingGroup Timers & PeripheralsStandard Generic GPIO verification (no fixed external spec)

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent GPIO pin driver, written clean-room against the pad-level contract — not derived from our own gpio RTL — so it functions as a true second source. Ships with a passive contract checker that verifies pull-up/pull-down pad contention and output-readback consistency (a symmetric delay line, not a same-cycle combinational compare), and a self-checking interop TB proving bit-loopback, the DSET/DCLR/DTGL atomic aliases, independent input, and both edge- and level-triggered interrupt modes against the catalog’s gpio. Covers per-pin input/output/interrupt behavior on a single-instance pad today — wake-from-low-power sequencing and multiplexed-pin sharing with the catalog’s SPI/I2C IP are a documented roadmap item, not yet built.

Key Features

Independent pin driver: DRIVE/PULSE_BIT task API on the pad’s input side
Passive contract checker: pull-up/pull-down pad contention, output-readback consistency via a symmetric delay line
Self-checking interop TB against the catalog’s gpio: bit-loopback proof, DSET/DCLR/DTGL aliases, independent input, edge- and level-mode IRQ — all pass
Scope today is single-instance per-pin I/O and interrupt behavior; wake-from-low-power and multiplexed-pin sharing are roadmap, not yet built

Standards & Compliance

Generic GPIO verification (no fixed external spec)

Pairs With

Built to lean against these catalog IPs during integration:

gpio

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Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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