JTAG / cJTAG

An independent IEEE-1149.1 JTAG TAP controller, written clean-room from the public TAP state-machine spec and the RISC-V External Debug Support (DTM) spec — not derived from our own jtag_dtm RTL — so it functions as a true second source. Drives the real jtag_dtm TAP over tck/tms/tdi/tdo and, through jtag_dtm’s own tck↔︎clk CDC, the real riscv_dm Debug Module over the DMI bus, proving the full TAP→DMI→DM path end to end (IDCODE read, DMI write/read-back of data0, dmcontrol/dmstatus register access). Ships with a passive DMI cross-checker that predicts the decoded bus request from the address/op the TB itself shifted into the DMI DR and flags any mismatch, plus a self-checking interop TB proving the checker catches an injected wrong prediction. Covers the standard IR opcodes (BYPASS, IDCODE, DTMCS, DMI) and DMI read/write/reserved-op handling — cJTAG (IEEE 1149.7) 2-wire mode, multi-TAP scan chains, and abstract-command/program-buffer execution on riscv_dm are a documented roadmap item, not yet built.

Key Features

• Independent IEEE-1149.1 TAP master: task-based RESET_TAP/IR_SCAN/DR_SCAN primitives plus IDCODE_READ/DMI_START/DMI_POLL DMI convenience wrappers
• Passive DMI cross-checker: predicts the decoded dmi_req_addr/dmi_req_op from the address/op the TB shifted into the DMI DR, flags illegal-op bus launches and undocumented safety err_codes
• Self-checking interop TB against the catalog’s real jtag_dtm → riscv_dm chain: IDCODE read-back, full DMI write+read round-trip through the CDC, reserved-DMI-op protocol-fault detection, and the lifecycle debug-enable gate — all pass
• Scope today is single-TAP JTAG (BYPASS/IDCODE/DTMCS/DMI, standard 4-wire) and riscv_dm‘s DMI-addressable register file; cJTAG 2-wire mode, multi-TAP chains, and abstract-command execution are roadmap, not yet built

Standards & Compliance

IEEE 1149.1, IEEE 1149.7 (cJTAG), RISC-V Debug Spec

Pairs With

Built to lean against these catalog IPs during integration:

• jtag_dtm
• riscv_dm