AMBA / On-Chip Bus

NoC / Multi-Protocol Fabric

Two independent TileLink-UL BFMs — a master (PUT/GET task API) and a slave/responder backing-memory model — written clean-room from the public TL-UL wire semantics, not from tl_xbar.sv…

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shippingGroup AMBA / On-Chip BusStandard Multi-protocol (AHB / AXI / APB / TileLink) fabric-level

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

Two independent TileLink-UL BFMs — a master (PUT/GET task API) and a slave/responder backing-memory model — written clean-room from the public TL-UL wire semantics, not from tl_xbar.sv, so they function as a true second source. Ships with a passive routing checker that cross-checks every accepted downstream beat against its own independent S_BASE/S_MASK copy — no address ever reaches the wrong slave port, no cross-master data leak — and a self-checking interop TB proving straight-path, cross-path, and genuinely concurrent (including same-slave-contended) multi-master traffic against the catalog’s tl_xbar. Covers TL-UL fabric routing at the crossbar’s default N_M=2/N_S=2 parameterization today; AXI-based NoC and CHI-based NoC fabric verification, along with wider N_M/N_S and TL-UH multi-beat bursts, are a documented roadmap item, not yet built.

Key Features

Independent TL-UL master BFM: single-outstanding PUT(addr,data)/GET(addr,out_data) task API
Independent TL-UL slave-responder BFM: simple backing-memory model, verbatim source-field echo for correct D-channel routing
Passive routing checker: address-based routing legality (own S_BASE/S_MASK copy) + cross-master attribution/data-leak checks, never reading DUT-internal state
Self-checking interop TB against the catalog’s tl_xbar: straight-path, cross-path, concurrent different-slave, and concurrent same-slave-contention traffic — all pass; TL-UL only at N_M=2/N_S=2, AXI/CHI-based NoC, wider fan-out, and TL-UH bursts are roadmap

Standards & Compliance

Multi-protocol (AHB / AXI / APB / TileLink) fabric-level

Pairs With

Built to lean against these catalog IPs during integration:

Interested in the NoC / Multi-Protocol Fabric VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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