Timers & Peripherals

PWM

An independent APB4 config master, written clean-room from the register map documented in the catalog’s own led_pwm RTL header comment — not derived from the RTL’s implementation — so it…

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shippingGroup Timers & PeripheralsStandard Generic PWM controller verification (no fixed external spec)

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent APB4 config master, written clean-room from the register map documented in the catalog’s own led_pwm RTL header comment — not derived from the RTL’s implementation — so it functions as a true second source. Ships with a passive duty/period checker that measures each pwm_out channel’s real high-time and period via edge detection and cross-checks them against the duty/period the TB itself configured, self-re-arming for the free-running waveform, and a self-checking interop TB proving two simultaneously-active channels at different duty ratios, a DUTY=0 boundary case, and a wrong-expectation injection against the catalog’s led_pwm. Covers the 4-channel (R/G/B/W) shared-period/prescaler LED-PWM contract today — mc_pwm (the motor-control PWM variant with complementary outputs and dead-time insertion) is a documented roadmap item, not yet built.

Key Features

Independent APB4 config master: WR/RD task API against the documented CTRL/PRESC/PERIOD/DUTY_x register map
Passive duty/period checker: predicts each channel’s high-time and period from the TB-issued duty/period values, never reading DUT-internal state, self-re-arming per period
Self-checking interop TB against the catalog’s led_pwm: two channels concurrently at different duty ratios (37.5%/75%), a DUTY=0 boundary case, and a wrong-expected-duty injection — all pass
Scope today is the shared-prescaler/period 4-channel (R/G/B/W) contract on one instance; mc_pwm‘s complementary/dead-time pairs are roadmap, not yet built

Standards & Compliance

Generic PWM controller verification (no fixed external spec)

Pairs With

Built to lean against these catalog IPs during integration:

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Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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