← All Verification IPAMBA / On-Chip Bus
SWD (Serial Wire Debug)
2-pin debug-transport verification for Serial Wire Debug — SW-DP register access and the DAP (Debug Access Port) command sequencing shared with JTAG-based debug.
plannedGroup AMBA / On-Chip BusStandard ARM Serial Wire Debug (SWD), ADIv5/ADIv6
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
2-pin debug-transport verification for Serial Wire Debug — SW-DP register access and the DAP (Debug Access Port) command sequencing shared with JTAG-based debug.
Key Features
- SW-DP request/acknowledge/data-phase transaction verification
- DAP (Debug Access Port) AP/DP register-access sequencing shared with the JTAG VIP
Standards & Compliance
ARM Serial Wire Debug (SWD), ADIv5/ADIv6
Pairs With
Built to lean against these catalog IPs during integration:
Interested in the SWD (Serial Wire Debug) VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
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