AXI4-Stream / AXI5-Stream

An independent TileLink-UL master plus a matched pair of AXI4-Stream SOURCE/SINK BFMs, written clean-room from the public TL-UL A/D-channel handshake and the generic AXI4-Stream TVALID/TREADY/TLAST/TKEEP convention — not derived from our own axi4s_bridge RTL — so together they form a true second source across both sides of the bridge. Ships with a passive AXI4-Stream protocol checker (one instance per direction) enforcing the classic no-valid-withdrawal rule plus payload/TLAST stability under stall, and a self-checking interop TB proving a TL-UL write drains out the AXI4-Stream master port, bytes pushed in on the AXI4-Stream slave port read back over TL-UL, TX-FIFO-full backpressure is correctly denied, and a directed injection the checker catches. Covers the single-outstanding TL-UL register front-end and the core TVALID/TREADY/TLAST/TKEEP handshake today — multi-outstanding TL-UL, TUSER sideband beyond a single bit, and burst DMA-descriptor modes are a documented roadmap item, not yet built.

Key Features

• Independent single-outstanding TileLink-UL master: PUT/GET task API exercising both PUT_FULL and PUT_PARTIAL opcodes
• Independent AXI4-Stream SOURCE (SEND_BEAT/SEND_PACKET) and SINK (RECV_BEAT/RECV_PACKET) BFMs driving/draining the stream ports directly
• Passive AXI4-Stream protocol checker (per direction): illegal TVALID withdrawal, TDATA/TKEEP stability under stall, TLAST framing consistency
• Self-checking interop TB against the catalog’s axi4s_bridge: TL-UL-to-stream drain, stream-to-TL-UL read-back, TX-FIFO-full denial, plus a directed injection caught by the checker — all pass

Standards & Compliance

ARM AMBA AXI4-Stream / AXI5-Stream

Pairs With

Built to lean against these catalog IPs during integration:

• axi4s_bridge