Camera & Display PHY (MIPI)

DSI v1.3.2

The catalog’s dsi_host is a TX-only host controller with no RX/BTA path modeled in this Technology-Preview revision…

shippingGroup Camera & Display PHY (MIPI)Standard MIPI DSI v1.3.2

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

The catalog’s dsi_host is a TX-only host controller with no RX/BTA path modeled in this Technology-Preview revision, so this VIP is a passive independent “panel” checker — written from the public DSI v1.3.2 packet spec — that watches the DUT’s real digital D-PHY Tx pins (dphy_data_o/valid_o/sot_o/eot_o; the electrical D-PHY layer itself is out of scope, matching dsi_host‘s own “Digital-only” scope) and independently decodes and re-validates command-mode DCS short/long-write packets and video-mode RGB888 packed-pixel-stream packets, recomputing DSI’s own 6-bit Hamming ECC and CRC-16/CCITT (a different bit-layout and polynomial convention than CSI-2’s, confirmed independently against a known-good vector). Since there is no DUT-side injection path for a TX-only host, the checker’s own teeth are proven via a muxed synthetic-packet injection. This second-source effort surfaced a real RTL finding, fixed 2026-07-09: the video-mode packetizer both truncated its own declared payload length to roughly 1/3 of what it promised, and assembled each transmitted RGB triplet from three DIFFERENT source pixels rather than one — both fixed by correcting the byte-vs-pixel-count comparison and gating the pixel-source pop to the packetizer’s own byte-emission cadence; this VIP’s own T4 now proves every triplet is clean and the payload length exactly matches the declared header.

Key Features

Independent passive panel/decoder: clean-room DSI 6-bit Hamming ECC + CRC-16/CCITT recompute, cross-checked against the DUT’s own transmitted header/CRC bytes
Command-mode coverage: DCS short write (0-param, 1-param) and long write, byte-exact payload verification
Video-mode coverage: RGB888 packed-pixel-stream framing, per-pixel RGB-triplet channel-coherency verification
A real video-mode packetizer bug was found and fixed (payload-length truncation + cross-pixel channel mixing, both now resolved) — see the write-up above

Standards & Compliance

MIPI DSI v1.3.2

Pairs With

Built to lean against these catalog IPs during integration:

dsi_host

Interested in the DSI v1.3.2 VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

Talk to us →See related VIP

Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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