Serial & Control Bus

I2C / I2S / LPC

An independent I2C master and slave/target pair, written clean-room from the NXP UM10204 specification — not derived from this catalog’s own i2c_master/i2c_slave RTL — so it functions as a…

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shippingGroup Serial & Control BusStandard NXP UM10204 I2C-Bus Specification

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent I2C master and slave/target pair, written clean-room from the NXP UM10204 specification — not derived from this catalog’s own i2c_master/i2c_slave RTL — so it functions as a true second source for interop testing. Ships with a passive protocol checker that asserts wire-level legality (SDA-stable-while-SCL-high, START/STOP framing, bus-free rules) independently of either agent’s FSM, and a self-checking interop TB proving master↔︎slave, master↔︎real-DUT, and injected-error detection all pass.

Key Features

Open-drain, clock-stretch-aware master (WRITE7/READ7 + bit/byte primitives) and reference slave/target
7-bit and 10-bit addressing
Passive protocol checker: SDA-stable-while-SCL-high, START/STOP framing, bus-free legality — independent of either agent’s FSM
Self-checking interop TB: master↔︎slave self-check, master↔︎catalog-i2c_slave interop, address decode, injected-error detection — all pass

Standards & Compliance

NXP UM10204 I2C-Bus Specification

Pairs With

Built to lean against these catalog IPs during integration:

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Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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