AMBA / On-Chip Bus

PLIC / CLIC / CLINT

Independent, clean-room second-source VIP for the RISC-V interrupt sub-system: an APB4 config master and interrupt-source stimulus driver exercise the real catalog plic RTL…

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shippingGroup AMBA / On-Chip BusStandard RISC-V Privileged Spec (Platform-Level Interrupt Controller)

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

Independent, clean-room second-source VIP for the RISC-V interrupt sub-system: an APB4 config master and interrupt-source stimulus driver exercise the real catalog plic RTL, while a passive routing checker re-derives the documented priority/enable/threshold eligibility contract straight from the shared bus and cross-checks ext_irq_o timing plus CLAIM-register arbitration against it every cycle — never by reading the DUT’s internal pending state. A companion clint interop TB covers the simpler mtime/mtimecmp/msip timer and software-interrupt registers the same way. Both self-checking testbenches include a directed fault-injection test proving their checkers actually catch a wrong expectation. CLIC is not yet covered — PLIC and CLINT are verified; CLIC is roadmap.

Key Features

Independent APB4 config BFM + interrupt-source stimulus BFM drive the real plic RTL directly — no shared code with the DUT
Passive routing checker re-derives priority/enable/threshold eligibility and its own pending-latch model from the bus, cross-checking ext_irq_o and CLAIM-id arbitration every cycle
Companion clint interop TB (mtime/mtimecmp/msip, tick-driven and software-write timer semantics) using the same independent-BFM-plus-passive-checker architecture
Both TBs include a directed injection test proving the checker catches a deliberately wrong expected-eligibility/timer state — make plic_oss / make clint_oss, each ending in ALL PASS

Standards & Compliance

RISC-V Privileged Spec (Platform-Level Interrupt Controller)

Pairs With

Built to lean against these catalog IPs during integration:

Interested in the PLIC / CLIC / CLINT VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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