QBV (Scheduled Traffic)

Focused 802.1Qbv Time-Aware-Shaper verification against tsn_switch‘s real GCL hardware: the independent checker tracks its own free-running gate-cycle counter and 4-entry Gate-Control-List purely from observed CSR writes (never the DUT’s registers) and cross-checks that an egress descriptor is never presented while its priority’s gate is independently computed CLOSED. The interop TB programs a small GCL (one priority open for part of the cycle, closed the rest) and proves a frame accepted during the closed window is held and only released once the schedule reopens — plus a directed injection proving the gate-legality check is enforced. Guard-band/gate-close frame-truncation scenarios are not applicable at this descriptor level (no in-flight byte truncation to model) and are roadmap only if a byte-level datapath is added.

Key Features

• Independent gate-cycle counter + GCL (interval/gate_states) model, rebuilt purely from observed GATE_CYCLE/GCL0..3 register writes — a second, independent implementation of the 802.1Qbv schedule decode, not a copy of the RTL’s
• Continuous cross-check: an egress descriptor must never be presented for a priority the checker independently computes gate-CLOSED at that cycle
• Interop TB proves a frame submitted during a closed window is correctly held and released only once the schedule reopens, fields intact
• Directed injection proves the gate-legality rule is actually enforced, not vacuously true; guard-band/frame-truncation scenarios are roadmap (no byte-level datapath at this descriptor abstraction)

Standards & Compliance

IEEE 802.1Qbv (Time-Aware Shaper)

Pairs With

Built to lean against these catalog IPs during integration:

• tsn_switch