Storage

SDUC / SDXC

Shares the same clean-room SD command/response + single-block DAT-transfer deliverable as vip-sdio (CMD0/CMD8/CMD1 init, CMD17/CMD24 single-block read/write…

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shippingGroup StorageStandard SD Physical Layer Specification (Ultra Capacity extensions) — command/response +…

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

Shares the same clean-room SD command/response + single-block DAT-transfer deliverable as vip-sdio (CMD0/CMD8/CMD1 init, CMD17/CMD24 single-block read/write, independent CRC7/CRC16 checker) against the catalog’s sdmmc controller, proving the core command/response and block-transfer protocol SDUC’s ultra-high-capacity addressing builds on top of. SDUC-specific ultra-high-capacity (>2TB) addressing and the associated CSD/extended-CSD register semantics are NOT exercised by this generic single-block test and remain roadmap.

Key Features

Independent card BFM proves the SDUC-shared CMD/RESP + single-block DAT protocol end-to-end against the real sdmmc host controller
Passive protocol checker independently re-validates CRC7/CRC16/framing legality on the wire, plus a directed CRC16 injection test
Ultra-high-capacity (SDUC) addressing and its CSD/CID register scenarios are NOT modeled — roadmap
Multi-block and 4-bit DAT-bus scenarios shared with the base SDIO/SDHC VIP are NOT modeled — roadmap

Standards & Compliance

SD Physical Layer Specification (Ultra Capacity extensions) — command/response + block-data layer only

Pairs With

Built to lean against these catalog IPs during integration:

sdmmc

Interested in the SDUC / SDXC VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space