Junction temperature for a flip-chip die on a silicon interposer, with the two heat paths resolved separately — up through TIM and lid, down through microbumps, interposer, substrate and board. It shows which layer dominates, what fraction of the heat actually goes each way, and the hot spot rather than the die average.
| Layer | Path | θ (K/W) | Rise at its share | % of its branch |
|---|
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A flip-chip die on an interposer has two ways to reject heat. Up through the die backside, the first thermal interface material, the lid and the heatsink; or down through the microbumps, the interposer, the C4 bumps, the substrate, the BGA and the board.
They are electrically in parallel, so the low-resistance branch carries almost all of the heat. With any reasonable heatsink the upward path is a fraction of a kelvin per watt and the downward path is several kelvin per watt — a ratio of ten or twenty to one. Ninety percent or more of the heat goes up.
That single fact decides where effort is worth spending. Elaborate thermal structures in the interposer or substrate change the average junction temperature very little when the lid is doing the work. The tool computes the split explicitly rather than leaving you to assume it.
It matters for everything that has no upward path of its own. On a typical 2.5D assembly the logic die sits under the heatsink and the HBM stacks sit beside it, sharing the same lid but with a worse interface and a taller stack of their own. Their heat has nowhere good to go, which is why memory bandwidth in these packages is so often thermally limited rather than electrically limited.
It also matters at power-down asymmetries: when the logic die is idle and the memory is not, the interposer becomes a lateral conduction path between neighbours rather than a vertical one, and a one-dimensional model of the kind here stops being the right tool.
θlayer = t / (k · A) ·
θJA = (θup · θdown) / (θup + θdown)keff = ksolder·f + kunderfill·(1−f),
with f the area fraction from pitch and diameter
Real dies are not uniform. A compute cluster or a SerDes bank can run several times the die average power density, and the local rise above the die average is set by the layers closest to the junction — the silicon and the TIM — because the heatsink is too far away and too spread out to see a millimetre-scale hot spot.
That is why the hot-spot figure here scales only the near-junction resistance. Thinning the die helps the average slightly and the hot spot a great deal, because it shortens the path before the heat has a chance to spread. It is also why TIM conductivity matters more than its datasheet position in the stack suggests.
The microbump layer is a composite: solder columns at maybe 20–25% area fraction, and underfill epoxy filling the rest. Solder conducts at around 58 W/mK and underfill at 0.5–0.9, so the effective conductivity is dominated by the bump fraction — which means bump pitch is a thermal parameter, not only an electrical one.
Push the pitch finer for bandwidth and the thermal path through the layer improves as a side-effect. Use a sparse bump field and the underfill dominates. Change the pitch above and that row of the table moves by tens of percent — and the junction temperature does not move at all, because with a good lid the bump layer is carrying almost no heat.
That is worth sitting with, because it is the general lesson of this page rather than an exception to it: a layer can be a large fraction of its own branch and still be irrelevant to the answer, if its branch is the one that lost. The bump layer only becomes a thermal design parameter when there is no upward path — under an HBM stack, in a lidless package, or when the heatsink is poor enough to even the two branches up. Set the heatsink to 10 K/W above and watch the split move to roughly a third upward; now the microbumps matter.
The board-side resistance in this model is a single lumped figure, and that is the part your PCB actually controls — copper area, via arrays under the BGA, and airflow. The thermal via calculator breaks that term down properly. And junction temperature feeds directly into reliability: the board FIT calculator shows what a 10 °C difference does to failure rate, which is usually a larger effect than anything in the component selection.
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