Camera & Display PHY (MIPI)

D-PHY v3.5

Both csi2_rx and dsi_host are explicitly digital-only Technology Preview IPs — each connects to an EXTERNAL D-PHY hard macro (Synopsys DWC_mipi_dphy, Cadence CDN-DPHY…

Request this VIP →Browse all VIP

shippingGroup Camera & Display PHY (MIPI)Standard MIPI D-PHY v3.5

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

Both csi2_rx and dsi_host are explicitly digital-only Technology Preview IPs — each connects to an EXTERNAL D-PHY hard macro (Synopsys DWC_mipi_dphy, Cadence CDN-DPHY, or similar) rather than implementing the electrical D-PHY layer itself, so this VIP’s real, honest scope is the DIGITAL byte-lane handoff interface both share — byte-parallel data, valid, SoT/EoT strobing, byte-clock domain — proven by the vip-csi2 and vip-dsi1 interop runs against the real DUTs. The electrical D-PHY layer itself (HS/LP differential signaling, lane-count bring-up, ULPS entry/exit) is genuinely out of scope for both catalog IPs in this revision, and therefore for this VIP too — shipping it here would misrepresent what either DUT, or this second-source effort, actually implements.

Key Features

Byte-parallel digital handoff interface verification (data/valid/SoT/EoT, byte-clock domain), shared by the vip-csi2 and vip-dsi1 deliverables
Single lane (LANES=1) — the tractable starting scope, matching this catalog’s other VIPs
Electrical D-PHY layer (HS/LP signaling, lane bring-up, ULPS) is explicitly out of scope, matching both catalog DUTs’ own “digital-only” scope

Standards & Compliance

MIPI D-PHY v3.5

Pairs With

Built to lean against these catalog IPs during integration:

Interested in the D-PHY v3.5 VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

Talk to us →See related VIP

Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space