AMBA / On-Chip Bus

AXI4 / AXI4-Lite / AXI3

A clean-room AXI4 master BFM written directly from the ARM AMBA AXI4 specification — not derived from our own bridge RTL or any vendor VIP — so it acts as a genuine second source when…

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shippingGroup AMBA / On-Chip BusStandard ARM AMBA AXI4 / AXI4-Lite / AXI3

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

A clean-room AXI4 master BFM written directly from the ARM AMBA AXI4 specification — not derived from our own bridge RTL or any vendor VIP — so it acts as a genuine second source when validating an AXI4-facing design. Ships with a task-based WRITE_BURST/READ_BURST API mirroring the shape of the commercial Cadence AXI4 master BFM this catalog also uses internally, so swapping between them in a testbench is a drop-in change.

Key Features

5-channel AXI4 handshake (AW/W/B/AR/R) with independent Valid/Ready timing
WRITE_BURST / READ_BURST task API — burst length, size, and address driven per call
EXPECT_RESP response checking (OKAY/EXOKAY/SLVERR/DECERR)
API-compatible task names with the Cadence cdn_axi4_master_bfm for easy swap-in

Standards & Compliance

ARM AMBA AXI4 / AXI4-Lite / AXI3

Pairs With

Built to lean against these catalog IPs during integration:

Interested in the AXI4 / AXI4-Lite / AXI3 VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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