← All Verification IP
Serial & Control Bus

SPI / QSPI / OSPI

An independent SPI master, written clean-room from the de facto 4-wire SCK/MOSI/MISO/CS_n convention — not derived from our own spi_master/spi_slave RTL — so it functions as a true second…

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shippingGroup Serial & Control BusStandard De facto flash-vendor conventions (Motorola/Macronix/Winbond/Micron/Samsung)

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model
An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.
Passive protocol checker
A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.
Self-checking interop testbench
A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent SPI master, written clean-room from the de facto 4-wire SCK/MOSI/MISO/CS_n convention — not derived from our own spi_master/spi_slave RTL — so it functions as a true second source. Ships with a passive protocol checker enforcing SCK-idle-while-deselected, CS-only-changes-while-SCK-low, and byte-multiple transfer framing, and a self-checking interop TB proving MOSI, MISO, and simultaneous full-duplex transfers against the catalog’s spi_slave. Covers Mode 0 (CPOL=0/CPHA=0, the reset default of both spi_master and spi_slave) and single-slave chip-select only today — the remaining CPOL/CPHA modes and Dual/Quad-I/O QSPI framing are a documented roadmap item, not yet built.

Key Features

Standards & Compliance

De facto flash-vendor conventions (Motorola/Macronix/Winbond/Micron/Samsung)

Pairs With

Built to lean against these catalog IPs during integration:

Interested in the SPI / QSPI / OSPI VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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