A companion to our walkthrough of the ASIC design flow. That article followed a chip from idea to silicon. This one follows a printed circuit board — the thing those chips get soldered onto — from concept to a fabricated, assembled, powered-up board on the bench. As with the chip flow, we cover the engineering; the physics inside the board-fab and assembly house is its own trade.
A PCB (printed circuit board) is the physical substrate that holds components and wires them together with etched copper. Designing one is its own pipeline — parallel in spirit to chip design, but with different tools, different failure modes, and a much shorter loop back to physical hardware. Below, each step lists what it does, its goal, and the tools, referencing the platforms that dominate professional PCB design: Cadence (Allegro / OrCAD), Siemens EDA (Xpedition / PADS / HyperLynx), Altium Designer, Zuken (CR-8000), and Ansys for signal- and power-integrity analysis.
1. Concept and requirements
What it does. Turns a product need into board-level requirements: what functions the board provides, the key components (processors, power, connectors, sensors), the interfaces and their speeds, mechanical constraints (size, mounting, connector positions), power budget, cost, and environment (temperature, vibration, compliance). For a safety- or reliability- critical board this is also where the hazard and derating requirements are set.
Goal. A clear specification and a rough architecture the rest of the flow can execute against — cheap to change now, expensive to change after layout.
2. Block diagram
What it does. Captures the board as functional blocks and the connections between them — power domains and rails, the main ICs, the high-speed and low-speed buses, clocking, and the external connectors — before drawing a single wire. It’s where the power tree and the interface topology get worked out.
Goal. A partitioning that’s electrically and mechanically sound, so the detailed schematic isn’t fighting a bad architecture.
3. Schematic capture — with libraries and 3D
What it does. Draws the full circuit: every component, every net, every value, on schematic sheets. This step leans heavily on component libraries, and getting them right is half the battle. Each part carries three linked views:
- a schematic symbol (how it appears on the schematic),
- a PCB footprint (the exact copper pads, courtyard, and dimensions the physical part solders to — get this wrong and the board is scrap), and
- a 3D model (so the board can be checked mechanically — height, clearance, connector and mounting-hole alignment against the enclosure).
Modern tools manage these as managed components tied to real manufacturer part numbers and live supply data. The schematic also drives the BOM (bill of materials — the parts list that will be ordered and assembled) and produces the netlist that hands connectivity to layout.
Goal. A complete, correct, reviewable circuit with trustworthy footprints and a clean netlist — the single source of truth the layout must match.
Tools.Cadence OrCAD / Allegro, Siemens PADS / Xpedition, and Altium Designer all provide integrated schematic capture, managed libraries, and linked 3D.
4. Board setup — stackup and constraints
What it does. Before placing anything, define the layer stackup (how many copper layers, their thicknesses, and the dielectric between them) and the design constraints. The stackup determines controlled impedance — the precise trace geometry needed so high-speed signals see a consistent impedance (e.g., 50 Ω single-ended, 100 Ω differential). Constraints capture trace widths, spacings, differential-pair rules, length-matching requirements, and clearances, so the layout tool can enforce them automatically.
Goal. A manufacturable stackup and a constraint set that encodes the electrical intent, so routing is correct by construction rather than by inspection.
5. Placement
What it does. Positions every component on the board. Placement is the single most consequential layout decision: it sets the length and feasibility of every subsequent route, the thermal behavior, the power-delivery path, and the mechanical fit. Connectors and mechanically-fixed parts land first (often driven by the enclosure via ECAD-MCAD co-design), then power, then the high-speed and sensitive analog sections are placed to keep critical nets short and quiet.
Goal. A placement that makes good routing possible, keeps power and heat manageable, and fits the mechanical envelope.
6. Routing
What it does. Draws the actual copper — the traces and vias that connect every net across the layers, honoring the constraints from step 4. High-speed work dominates the effort: length-matching buses so bits arrive together, routing differential pairs with controlled spacing, maintaining reference planes for clean return paths, and managing the copper pours and power planes that deliver current. Low-speed and power nets are routed around them.
Goal. Every net connected, every high-speed rule met, with clean power delivery and return paths — a physically complete board.
Tools.Cadence Allegro X, Siemens Xpedition, Altium Designer, and Zuken CR-8000 are the professional layout environments.
7. Signal and power integrity (SI/PI)
What it does. Verifies the board electrically before it’s built. Signal integrity checks that high-speed signals arrive clean — impedance is controlled, reflections and crosstalk are bounded, and eye diagrams close on multi-gigabit links. Power integrity checks that the power-delivery network holds voltage steady under load — the plane impedance, decoupling, and IR-drop are adequate. On the fastest interfaces this extends to full electromagnetic modeling of the channel.
Goal. Confidence that the board will work at speed, not just connect correctly — before committing to fabrication.
Tools.Siemens HyperLynx and Ansys SIwave / HFSS; Cadence provides integrated SI/PI within the Allegro platform.
8. DFM, DFA, and design-rule checks
What it does. The gate before release. DRC (design-rule check) verifies the layout obeys the electrical and spacing rules. DFM (design for manufacturability) checks the board can actually be fabricated reliably — trace/space minimums, annular rings, solder-mask slivers, acid traps, copper balance. DFA (design for assembly) checks it can be assembled — adequate component spacing, correct courtyards, thermal reliefs, fiducials for the pick-and-place machine, and testability access. Catching these here is the difference between a clean build and a scrapped panel.
Goal. A design proven manufacturable and assemblable, not just electrically correct.
Tools. DFM/DFA analysis is built into Siemens, Cadence, and Altium; many teams also run a dedicated DFM check against their fab house’s specific capabilities.
9. Manufacturing outputs — export to the fab house
What it does. Generates the complete data package the board house and assembler consume: the copper, mask, and silkscreen layers as Gerber files (or the richer, single-file ODB++ / IPC-2581 formats), the drill files, the BOM, the pick-and-place (centroid) file that tells the assembly machine where each part goes, the assembly drawings, and the fabrication notes and stackup. This package is the board’s equivalent of a chip’s GDSII handoff.
Goal. A complete, unambiguous manufacturing dataset — so the board that comes back is the board you designed.
10. Fabrication and assembly
The board house etches the copper, laminates the stackup, drills and plates the vias, and applies mask and silkscreen; the assembler then solders the components — stencil, place, reflow. The chemistry and machinery of that are a separate discipline this article doesn’t cover. But engineering resumes the moment the boards come back.
11. Incoming inspection — what comes back
What it does. Before trusting a returned board, verify the build. AOI (automated optical inspection) and, for hidden joints like BGAs, X-ray inspection check that components are present, correct, and well-soldered. Bare-board and assembled electrical tests — flying-probe or ICT (in-circuit test) — check for shorts, opens, and wrong values against the netlist. This screens out fabrication and assembly defects before they waste bring-up time.
Goal. Confidence that a board that fails on the bench failed by design, not by a bad solder joint — so debugging targets the right thing.
12. Board bring-up
What it does. Power the board for the first time — carefully. Bring-up proceeds in order: check power rails come up correctly and in sequence (often current-limited at first), confirm clocks and resets, then boot the firmware and exercise each interface. Problems are localized with the schematic, an oscilloscope and logic analyzer, and the board’s test points and debug headers. Findings feed back: a respin-worthy bug drives a board revision, a fixable one may be patched with a rework wire.
Goal. A board proven to power up, run its firmware, and meet its functional and performance requirements — the payoff of the whole flow.
Optional overlay — the ISO 26262 functional-safety flow for boards
If the board goes into a car — or any system where a malfunction can hurt someone — the flow above is necessary but not sufficient. ISO 26262 (“Road vehicles — Functional safety”) requires a parallel set of board-level activities that run alongside every step, each producing its own evidence, all assembled into a safety case. This is the same discipline our ASIC flow article covers at the chip level, applied to the printed circuit board — the redundancy, monitoring, and component discipline happen in copper and components instead of RTL.
The rigor scales with the ASIL (Automotive Safety Integrity Level), A (least) to D (most stringent). ASIL B and ASIL D are the common targets, and the quantitative bars the hardware must clear differ sharply:
| Metric | What it means | ASIL B | ASIL D |
|---|---|---|---|
| SPFM (single-point fault metric) | fraction of faults covered by a safety mechanism or safe by design | ≥ 90% | ≥ 99% |
| LFM (latent-fault metric) | fraction of undetected faults a second mechanism still catches | ≥ 60% | ≥ 90% |
| PMHF (probabilistic metric for random hardware failures) | residual dangerous-failure rate, in FIT (failures per 10⁹ h) | < 100 FIT | < 10 FIT |
Each activity below notes where it hooks into the standard board flow.
PS1. Item definition, HARA and safety goals(hooks into step 1) — the HARA (Hazard Analysis and Risk Assessment) identifies hazards and rates them on severity, exposure, and controllability, which determines the ASIL and yields the top-level safety goals. Tools:Ansys medini analyze.
PS2. Technical safety requirements allocated to the board(hooks into steps 1–2) — the safety goals are refined into concrete, traceable hardware requirements assigned to specific parts of the board (this rail, this monitor, this redundant channel).
PS3. Safety mechanisms on the board(hooks into step 3, schematic) — the board actively detects and reacts to faults: voltage/current supervisors, a window watchdog, safe-state control (e-fuse, safe shutdown), redundant or diverse-redundant channels, and decoupling/monitoring on critical rails. These are the board-level analogue of a chip’s ECC and lockstep.
PS4. Board-level FMEDA(hooks into steps 3–6) — the FMEDA (Failure Modes, Effects, and Diagnostic Analysis) enumerates each component’s failure modes, assigns base failure rates from reliability handbooks (SN 29500, IEC 62380, or FIDES), credits each safety mechanism with a diagnostic coverage, and rolls the result up into SPFM, LFM, and PMHF to check against the ASIL targets above. Tools: medini analyze; Ansys Sherlock / ReliaSoft for the component FIT data.
PS5. DFMEA, FTA and dependent-failure analysis (DFA)(hooks into step 5, placement) — a board has strong common-cause risks the FMEDA’s independence assumption misses: a shared supply rail, a shared clock, thermal coupling, or two “redundant” parts sitting next to each other. DFMEA, FTA, and DFA hunt these out and drive mitigations — most importantly physical separation on the board for freedom from interference. This is why safety matters so much at placement.
PS6. Component qualification and derating(hooks into step 3, BOM) — safety-relevant parts must be automotive-qualified (AEC-Q100 for ICs, AEC-Q200 for passives, AEC-Q101 for discretes) and used within conservative derating limits (voltage, current, temperature, power) so they stay reliable across the mission profile.
PS7. Reliability and thermal analysis(hooks into steps 5–7) — a physics-of-failure and thermal analysis predicts wear-out mechanisms (solder-joint fatigue, via cracking, electrolytic-cap aging) and confirms every part stays within its thermal derating, feeding the FMEDA’s base failure rates. Tools:Ansys Sherlock for physics-of- failure and thermal.
PS8. Safety validation, confirmation reviews and safety case(hooks in before step 9, fab release) — the evidence — HARA, requirements traceability, board FMEDA, DFA, qualification and derating records, reviews — is assembled into an auditable safety case, with independent confirmation reviews signing it off before release.
The board and the chip share one safety story. The strongest safety case is one where the IP inside the chip already carries its own ISO 26262 work products, so the board-level FMEDA can credit them directly instead of treating each chip as an opaque black box. That’s exactly what our safety soft-IP provides — and we design the safety-aware boards those chips live on.
PCB vs. ASIC: the same shape, a shorter loop
The board flow rhymes with the chip flow — specification, capture, physical implementation, verification, a manufacturing handoff, and bring-up — but two things differ sharply. First, the loop is far shorter and cheaper: a board respin is days-to-weeks and hundreds-to-thousands of dollars, versus months and millions for silicon, so the discipline can be a little more iterative. Second, the physical design is placement-and-routing on a handful of copper layers rather than billions of transistors, so a human designer stays hands-on throughout. Both, though, live or die on the same things: correct libraries/IP, controlled impedance and clean power, and verification before you commit to manufacturing.
Where we fit
We design at both levels — the safety soft-IP that goes inside the chip, and the boards and systems those chips live on: schematic, high-speed layout, signal and power integrity, and bring-up. If you have a board or system that needs to be designed, verified, and brought up — or IP that needs to drop cleanly into one — that’s what we do. See circuit-design.space.
Glossary
AOI — Automated Optical Inspection. Camera-based checking of assembled boards for placement and solder defects.
BOM — Bill of Materials. The parts list — every component, value, and part number — to be ordered and assembled.
Controlled impedance — Trace geometry engineered so a high-speed signal sees a specified, constant impedance (e.g., 50 Ω / 100 Ω).
Copper pour — A filled copper region, typically a power or ground plane.
DFA — Design for Assembly. Ensuring the board can be assembled reliably (spacing, courtyards, fiducials, thermal reliefs).
DFM — Design for Manufacturability. Ensuring the board can be fabricated reliably (trace/ space minimums, annular rings, copper balance).
Differential pair — Two coupled traces carrying complementary signals, routed with controlled spacing for high-speed links.
DRC — Design Rule Check. Automated verification that the layout obeys its electrical and spacing rules.
ECAD-MCAD — The link between electrical (board) and mechanical (enclosure) design, for fit and clearance.
Fiducial — A reference mark the pick-and-place machine uses to locate the board.
Footprint — The exact copper pads and outline a physical component solders to.
Gerber — The classic per-layer file format handed to the board fabricator.
ICT — In-Circuit Test. A bed-of-nails fixture that electrically tests an assembled board.
Length matching — Adjusting trace lengths so related signals arrive together.
Netlist — The connectivity (which pins connect to which nets) exported from the schematic to layout.
ODB++ / IPC-2581 — Richer, single-file manufacturing formats that carry more intent than raw Gerbers.
Pick-and-place (centroid) — The file giving each component’s position and rotation for the assembly machine.
PI (power integrity) — Analysis that the power-delivery network holds voltage steady under load.
Reflow — The soldering process: solder paste is applied, parts placed, then the board heated to melt and form the joints.
SI (signal integrity) — Analysis of reflections, crosstalk, and timing on high-speed signals.
Silkscreen — The printed labels and outlines on the board surface.
Solder mask — The protective coating (usually green) that exposes only the pads to be soldered.
Stackup — The arrangement of copper and dielectric layers that makes up the board.
Via — A plated hole connecting copper on different layers.
X-ray inspection — Imaging of hidden solder joints (e.g., under BGAs) to verify assembly.
Functional-safety terms (ISO 26262)
AEC-Q100 / Q200 / Q101 — Automotive qualification standards for ICs, passive components, and discrete semiconductors respectively.
ASIL — Automotive Safety Integrity Level (A–D). ISO 26262’s risk classification; D is the most stringent, and it sets the quantitative safety targets the hardware must meet.
Derating — Operating a component well within its rated limits (voltage, current, temperature, power) to improve reliability over the mission profile.
DFA (safety sense) — Dependent-Failure Analysis: finding common-cause and cascading faults that defeat redundancy (shared supply, clock, thermal region, or physical proximity). Note: in layout, “DFA” also means Design for Assembly — a different concept.
FIT — Failures In Time: one FIT is one failure per 10⁹ operating hours. The unit for PMHF and component base failure rates.
FMEDA — Failure Modes, Effects, and Diagnostic Analysis. The quantitative ISO 26262 analysis that computes SPFM, LFM, and PMHF from component failure rates and diagnostic coverage.
Freedom from interference — Assurance that a fault in one element cannot propagate to corrupt another; on a board, achieved largely through physical separation.
HARA — Hazard Analysis and Risk Assessment. Identifies hazards and rates them, determining the ASIL and the safety goals.
ISO 26262 — The automotive functional-safety standard governing electrical/electronic systems in road vehicles.
LFM — Latent-Fault Metric. The fraction of undetected faults still caught by a second mechanism.
PMHF — Probabilistic Metric for random Hardware Failures. The residual dangerous-failure rate (in FIT) a design must stay under.
Safe state — A defined condition the system is driven to when a fault is detected, so the fault doesn’t propagate to a hazard.
Safety case — The assembled, auditable body of evidence arguing a design is acceptably safe.
Safety mechanism — Hardware (supervisor, watchdog, redundancy, e-fuse…) that detects or controls faults so they don’t cause a hazard.
SPFM — Single-Point Fault Metric. The fraction of faults covered by a safety mechanism or safe by design.
Further reading — reference books
- Howard Johnson & Martin Graham, High-Speed Digital Design: A Handbook of Black Magic — the classic on SI and high-speed layout.
- Eric Bogatin, Signal and Power Integrity — Simplified.
- Henry Ott, Electromagnetic Compatibility Engineering — grounding, shielding, EMC.
- Lee Ritchey, Right the First Time: A Practical Handbook on High-Speed PCB and System Design.
- Clyde Coombs & Happy Holden, Printed Circuits Handbook — the encyclopedic reference on fabrication and assembly.
- Mark Montrose, EMC and the Printed Circuit Board.
- ISO 26262:2018, Road vehicles — Functional safety (Parts 5 and 9 for hardware).
Have a board or system to design, verify, or bring up? That’s what we do. Reach us at circuit-design.space.
circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space