The IF Chain and the ADC: Where Dynamic Range Is Won or Lost

Part of the RF chain series — a page per block. The IF chain follows the mixer and ends the analogue signal path.

The RF chain, block by block —Antenna · Filter · LNA · Mixer · LO · IF & ADC · PA · Isolator · Coupler · Overview

By the time a signal reaches the IF chain, the LNA has set the noise figure and the mixer has set most of the linearity. What is left is the job of presenting the signal to the ADC at exactly the right amplitude, with everything outside the band removed — and that turns out to be where most receivers actually run out of dynamic range.

1. The gain-distribution problem

The ADC wants a signal that nearly fills its input range. The antenna delivers something between −110 dBm and −10 dBm depending on conditions. The IF chain has to bridge that, and where you put the gain decides everything:

• Too much gain too early and a strong interferer compresses a stage before the filtering that would have removed it.
• Too little gain early and the later stages’ noise degrades the figure the LNA worked for — the Friis cascade again, now with the mixer’s loss in front.
• Too much total gain and the ADC clips on peaks.
• Too little and you waste ADC bits on empty range.

The resolution is filter early, amplify after: each filter removes interferers so the next amplifier can have gain without compressing. Gain and selectivity alternate down the chain.

Automatic gain control then handles the remaining range. The design questions are its attack and decay time constants, whether it is stepped or continuous, and where it takes its detector from. Too fast and it modulates the signal itself; too slow and it clips on a sudden strong burst.

How much gain, exactly

The question has a definite answer, and it comes from treating the ADC as just another stage with a noise figure. An ADC’s noise figure is:

$$\mathrm{NF}_{\text{ADC}} \approx P_{\text{FS}}\ [\mathrm{dBm}] – \mathrm{SNR}\ [\mathrm{dB}] – 10\log_{10}\!\left(\frac{f_s}{2}\right) + 174$$

and the result is remarkably consistent across very different converters:

An ADC is a 25–30 dB noise figure device. That is a terrible stage to put at the end of a receiver — and the Friis cascade says the fix is gain in front of it. With a 5 dB front end:

Thirty to forty decibels of gain ahead of the ADC is the number, and beyond that you are paying for nothing. That is the single most useful sizing result on this page, and it is why receivers have as much IF gain as they do.

And how much headroom

Total gain is then bounded from above by clipping, and the bound is set by the signal’s peak- to-average ratio. Full scale on a typical differential converter input:

So for a +7 dBm full scale:

(each allowing 3 dB of margin for AGC overshoot and blockers). The gain that maximises SNR and the gain that avoids clipping are different numbers, and the AGC’s job is to sit between them — which is why the AGC’s target level, not just its time constants, is a design decision worth making deliberately.

2. What the ADC actually gives you

The ideal SNR of an $n$-bit converter, quantisation noise only:

$$\mathrm{SNR} = 6.02n + 1.76\ \mathrm{dB}$$

No real converter achieves this. The honest figure comes from measured SINAD (signal-to-noise-and-distortion), converted back into bits as ENOB:

$$\mathrm{ENOB} = \frac{\mathrm{SINAD} – 1.76}{6.02}$$

Always design to ENOB at your input frequency, never to the nameplate bit count. A “14-bit” converter delivering 68 dB SINAD is an 11-bit converter, and the gap grows with input frequency for the reason in the next section.

SFDR — spurious-free dynamic range — is a separate and often more binding number. It is the distance from the carrier to the largest spur, and for a receiver that must detect a weak signal in the presence of a strong one, SFDR rather than SNR is the limit. SNR is a noise floor; SFDR is a discrete tone that can look exactly like a signal.

3. Aperture jitter, the thing that actually limits high-IF sampling

An ADC samples at instants defined by its clock. If those instants wobble by $\sigma_t$, a signal that is slewing gets sampled at slightly the wrong voltage — and the faster it slews, the bigger the error:

$$\mathrm{SNR}_{\text{jitter}} = -20\log_{10}(2\pi f_{\text{in}} \sigma_t)$$

The input frequency is in there, not the sample rate. Sampling a 100 MHz IF demands ten times better clock jitter than sampling a 10 MHz IF for the same SNR. This is the practical ceiling on direct RF sampling, and it is why the ADC’s clock is an RF design problem, not a digital one — see the LO and synthesis page, since phase noise and jitter are the same quantity in different coordinates.

Jitter does not replace the converter’s own noise; it adds to it. Combining the two — a 14-bit-class converter with 69 dB of intrinsic SNR — shows where each one is in charge:

Read across the top row: at a 100 MHz IF, going from 200 fs to 50 fs buys half a decibel, and the jitter-cleaning chip that achieves it is wasted money. Read down the right column: at 2 GHz, 50 fs still costs 6 dB against the converter’s own capability, and you would need 25 fs to stop losing. Which mechanism dominates depends entirely on the input frequency, so the first thing to do when an SNR measurement disappoints is work out which side of that boundary you are on — the fix is completely different in each case.

The clock path deserves the same care as the signal path: low-jitter source, a clean supply (see power integrity), and no digital crosstalk onto the clock net. Two specifics worth stating: the clock’s slew rate at the ADC pin matters as much as its jitter, because the converter’s own comparator converts voltage noise into timing noise in proportion to $1/(dV/dt)$ — a slow or attenuated clock edge manufactures jitter inside the part. And the ADC’s own aperture jitter sets a floor that no external clock beats; check the datasheet number before specifying a clock cleaner better than it.

4. Process gain: bandwidth you do not use is SNR you do

Quantisation noise is spread across the whole Nyquist band. If your signal occupies only part of it, digital filtering discards the rest of the noise:

$$G_p = 10\log_{10}\!\left(\frac{f_s/2}{\mathrm{BW}}\right)$$

Oversampling by 4× buys 6 dB — one bit. It is the cheapest dynamic range available, and it is why high-speed converters are used well beyond the Nyquist requirement.

5. Anti-aliasing, and the useful trick

Anything above $f_s/2$ folds back into the band indistinguishably from real signal. The anti-alias filter must remove it before sampling, because no amount of DSP recovers from aliasing.

The filter’s required rejection is the ADC’s dynamic range — there is no point having 80 dB of SFDR if an out-of-band signal aliases in at −60 dBFS. That sets the order, via the filter arithmetic, and the transition width available is set by the gap between your signal band and $f_s/2$.

Undersampling (bandpass sampling) turns the folding into a feature: sample a signal centred well above $f_s/2$ and let it alias deliberately down to a low frequency. The sample rate needs only to exceed twice the signal bandwidth, not twice its highest frequency, and the anti-alias filter becomes a bandpass rather than a lowpass. The catch is aperture jitter, which still scales with the actual input frequency, and the ADC’s input bandwidth must genuinely extend that high.

The bookkeeping is the Nyquist zone. At $f_s = 1$ GSPS:

Even zones come out mirrored, which means I and Q swap sign, an offset tunes the wrong way, and a perfectly good demodulator produces nonsense. It is a one-line fix in the DSP and a frustrating afternoon if nobody expected it. Sketch the zone diagram before fixing the sample rate, exactly as you would sketch the mixer’s spur chart before fixing an IF — it is the same discipline applied to a different folding mechanism.

6. Interleaving spurs, on any converter above about 1 GSPS

Most very fast converters are not one converter. They are $M$ slower cores sampling in rotation, and any mismatch between the cores produces spurs at predictable frequencies:

Worked, for a 4-way interleaved 1 GSPS converter with a 240 MHz input: offset spurs land at 250, 500 and 750 MHz; gain and timing spurs land at 10 MHz, 260 MHz and 510 MHz. The first of those sits 230 MHz from the carrier but could be inside a wide signal band — and unlike harmonic distortion, it does not move when you back off the input level.

Two things follow. Offset spurs are distinguishable from real signals by not moving when you tune the input, which is the diagnostic. And the fix is calibration, not layout: modern parts have on-chip interleaving correction that must be run at the operating temperature and sample rate, and a converter whose spurs look wrong is often simply one whose calibration was never triggered.

7. Direct RF sampling

Modern GSPS converters can digitise the RF directly, deleting the mixer and IF chain entirely. The trades:

Direct RF sampling wins where flexibility and channel count matter — phased arrays, software- defined radio, test equipment — and loses on power. A battery-powered receiver still uses a mixer.

8. A design method

1. Work out the required dynamic range from the weakest signal and the strongest interferer that must coexist.
2. Choose the ADC on ENOB and SFDR at your input frequency, not on bit count.
3. Compute the jitter budget from the input frequency and the SNR target, and specify the clock accordingly.
4. Distribute gain, alternating with filtering, so no stage compresses before the filter that protects it.
5. Design the anti-alias filter to the ADC’s dynamic range, not to a round number.
6. Add process gain by oversampling where the power budget allows.
7. Design the AGC loop dynamics against the real signal statistics.
8. Treat the clock and the supplies as RF, because they are.
9. Measure SINAD and SFDR on the real board at the real input frequency.

9. Example parts

The IF chain is three kinds of part — a variable-gain amplifier, a driver, and the converter — plus the clock, which is covered on the LO page. Illustrative; check availability.

Variable-gain and digitally controlled amplifiers:

ADC drivers — differential, with the right common mode, and enough linearity not to be the thing that limits SFDR:

A transformer or balun is the alternative and is often better: no noise, no distortion, no power, and excellent common-mode rejection — at the cost of no gain and no DC path. Look at Mini-Circuits TC-series baluns and Mini-Circuits/Anaren RF transformers before assuming an active driver is required.

Converters — the choice is nearly always ENOB and SFDR at the real input frequency, then power:

The single most useful habit when choosing: find the SNR and SFDR plots versus input frequency in the datasheet, not the summary table. The front page quotes performance at a low input frequency; your signal is not there, and the difference between the two is frequently several effective bits.

10. The pitfalls

• Designing to nameplate bits instead of measured ENOB — and reading ENOB at the datasheet’s input frequency rather than yours.
• A clean ADC fed by a jittery clock — the most common cause of disappointing SNR.
• Chasing clock jitter when the input frequency is low enough that it was never the limit.
• A slow or attenuated clock edge at the ADC pin, manufacturing jitter inside the part.
• Too little gain ahead of the ADC, so its 25–30 dB noise figure lands on the system.
• An anti-alias filter specified by rule of thumb rather than by the converter’s dynamic range.
• Sampling in an even Nyquist zone and not expecting the spectral inversion.
• Interleaving spurs on a fast converter whose calibration was never run at temperature.
• All the gain in one place, so one interferer compresses everything.
• SFDR ignored because SNR looked adequate — a spur is not noise, and it looks like a signal.

Further reading

• Walt Kester (ed.), The Data Conversion Handbook. Free from Analog Devices and also in print; the source for the ADC noise-figure and jitter arithmetic above.
• Walt Kester, Mixed-Signal and DSP Design Techniques. Grounding, layout and the interface between the analogue and digital worlds.
• Richard Lyons, Understanding Digital Signal Processing. The clearest explanation of Nyquist zones, bandpass sampling and spectral inversion in print.
• Behzad Razavi, Principles of Data Conversion System Design. What is going on inside the converter, if the black-box view stops being enough.
• Hank Zumbahlen (ed.), Linear Circuit Design Handbook. For the driver, the filter and the reference around the converter.
• Digital switching noise coupled into the clock or the analogue supplies.
• Undersampling with a converter whose input bandwidth does not reach the signal.
• AGC time constants chosen by default, then modulating the signal.

The RF chain, block by block —Antenna · Filter · LNA · Mixer · LO · IF & ADC · PA · Isolator · Coupler · Overview

Glossary

ADC noise figure — $P_{\text{FS}} – \mathrm{SNR} – 10\log_{10}(f_s/2) + 174$, and remarkably consistent at 25–30 dB across very different converters. Treating the ADC as just another cascade stage is what tells you how much gain belongs in front of it: 30–40 dB, and beyond that you are paying for nothing.

AGC — Automatic gain control, bridging the range between the weakest signal and the strongest. Its target level is as much a design decision as its time constants, because the gain that maximises SNR and the gain that avoids clipping are different numbers.

Anti-alias filter — The filter removing everything that would fold in. Its required rejection is the converter’s dynamic range, not a round number — there is no point having 80 dB of SFDR if an out-of-band signal aliases in at −60 dBFS.

Aperture jitter — Uncertainty in the sampling instant, giving $\mathrm{SNR} = -20\log_{10}(2\pi f_{\text{in}}\sigma_t)$. The input frequency is in there, not the sample rate, which is why a 14-bit converter sampling a 1 GHz input needs under 50 fs to deliver 11 effective bits.

dBFS — Decibels relative to full scale. The natural unit for everything inside the converter, and the one that makes a headroom budget legible: a 10 dB-PAPR signal with 3 dB of margin runs at −13 dBFS average.

Dither — Deliberately added noise that decorrelates quantisation error from the signal, trading a little SNR for markedly better SFDR. Worth it whenever a spur matters more than a noise floor, which in a receiver is most of the time.

ENOB — Effective number of bits, $(\mathrm{SINAD} – 1.76)/6.02$. The honest resolution: a “14-bit” converter delivering 68 dB SINAD is an 11-bit converter, and the gap widens with input frequency.

Full scale ($P_{\text{FS}}$) — The input power that just fills the converter, about +7 dBm for 2 V peak-to-peak differential into 100 Ω. The reference every headroom calculation is made against.

Interleaving spur — Artefacts from an $M$-way interleaved converter’s channel mismatches: offset spurs at $kf_s/M$ that do not move with the input, gain and timing spurs at $kf_s/M \pm f_{\text{in}}$ that do. Not moving when you tune the input is the diagnostic, and the fix is calibration rather than layout.

Nyquist zone — Which $f_s/2$ band the input occupies. Even zones arrive spectrally inverted after sampling, which is a one-line fix in the DSP and a frustrating afternoon if nobody expected it.

Process gain — $10\log_{10}(f_s/2\mathrm{BW})$: the SNR recovered by filtering away the quantisation noise outside your signal band. Oversampling 4× buys 6 dB, one bit, and it is the cheapest dynamic range available.

SFDR — Spurious-free dynamic range: the distance to the largest spur. Often more binding than SNR, because a noise floor hides a weak signal while a spur looks like one.

SINAD — Signal to noise and distortion, measured rather than derived. The input to ENOB, and the number to read off the datasheet’s plot against input frequency rather than off its front page.

Undersampling (bandpass sampling) — Deliberately letting a signal above $f_s/2$ alias down. The sample rate need only exceed twice the signal bandwidth, and the anti-alias filter becomes a bandpass — but aperture jitter still scales with the real input frequency, which is what limits it.

Related

• The RF chain overview
• The mixer in front — what lands in the IF, wanted and not
• The local oscillator — phase noise is the clock’s jitter
• Filters — anti-aliasing and channel selectivity
• Power integrity — supply noise on a converter is dynamic range

Have a receiver that will not reach its dynamic range, or an ADC underperforming its datasheet? That’s what we do. Reach us at circuit-design.space.