Free tools

Engineering tools

Calculators we built because we needed them. Each one runs entirely in your browser — nothing is uploaded, nothing is stored, and none of them asks for an email address.

Functional safety

ASIL determination →
Severity, exposure and controllability to an ASIL, with the reasoning shown.
FIT & PMHF budget →
Failure rate and diagnostic coverage to SPFM, LFM and PMHF for one element.
FMEDA rollup →
Many elements rolled up to system SPFM, LFM and PMHF, ranked by contribution.
Solder joint fatigue →
Coffin-Manson thermal cycling life, scaled from a qualification test.
Board FIT from a BOM →
Component counts and a mission profile to a board-level failure rate and MTBF.
Creepage and clearance →
Required spacing from working voltage, pollution degree, CTI and overvoltage category.
FMEA action priority →
Severity, occurrence and detection triaged by precedence — and why RPN was retired.
ASIL decomposition →
Every permitted split of a safety goal, and the independence the DFA has to demonstrate.
Safety mechanism selector →
Which mechanism suits a region, what it is blind to, and whether the coverage reaches the target.
FTTI timing budget →
Worst-case detection latency and reaction against the fault tolerant time interval.

Power and thermal

PDN target impedance →
Ripple and transient current to a target impedance, decap count and bulk capacitance.
Decoupling impedance plot →
Plots the anti-resonance peaks between capacitor self-resonances that flat models hide.
Buck converter design →
Inductor, output and input capacitance from the operating point. Vendor-neutral.
Interposer thermal (2.5D) →
Flip-chip on interposer: both heat paths resolved, every layer ranked, hot spot.
Radiated emissions →
Cable common-mode and loop radiation against CISPR and FCC limits, swept.
Capacitor life and ripple →
Ripple self-heating and Arrhenius life -- every 10 degC halves it.
Inrush and soft-start →
Peak current, switch energy and SOA -- the energy is fixed, only time is yours.
Thermal via array →
Junction temperature from theta-JC, a plated via array and spreading copper.
LED ballast resistor →
Ballast value and the current spread across supply, Vf binning and temperature.
Trace width (IPC-2152) →
Current to trace width, showing where the obsolete IPC-2221 formula gets it wrong.
Trace IR drop and rise →
Resistance, voltage drop against the rail budget, and temperature rise.
Battery technology selector →
Operating envelope to a ranked chemistry — filtered on pulse droop and charge temperature, not just energy density.
Battery life estimator →
Duty-cycled load profile to runtime, with self-discharge and the dominant mode ranked.

Analog and signal integrity

Via stub resonance →
Stub length to its quarter-wave null, and whether the link needs backdrilling.
Resistor divider →
E-series values, worst-case output range with stacked tolerances, and dissipation.
Op-amp error budget →
Every DC error term referred to the input, ranked, and converted to ADC LSBs.
Signal chain noise →
Per-stage noise referred to the input, the stage that sets the floor, and ENOB.
Phase noise to jitter →
Integrate an L(f) profile to RMS jitter, with the dominant decade named.
TVS / ESD clamp →
Real clamp at the actual surge current, plus the L.di/dt your layout adds.
Crystal load and margin →
C1/C2 from the specified load, plus startup gm margin and crystal drive level.
NEXT / FEXT crosstalk →
Near and far-end coupling from geometry, swept against spacing, with the 3W point.
BER, jitter and eye →
Bit error ratio mapped to Q, jitter, eye opening and BERT run time, with a bathtub.
Channel loss and reach →
Dielectric and conductor loss per inch, and how many inches the budget actually buys.
DDR / timing budget →
Setup and hold margin with every consumer of the unit interval ranked.
Differential pair skew →
Intra-pair skew against the unit interval and the edge, including fibre weave.
Current sense shunt →
Shunt value, dissipation and the error stack at both full scale and minimum current.
Comparator hysteresis →
Trip points to real E-series resistors, with a noise-immunity check.
PCB stackup planner →
Layer count from BGA escape, laminate from your fastest signal, and the widths that follow.
PCB DFM checker →
Annular ring, aspect ratio, drill-to-copper and BGA escape vs capability bands.
Trace impedance + sweep →
Microstrip, stripline and differential, with a Z-vs-geometry plot and tolerance stack.
RC / LC filter designer →
Corner frequency from real E-series parts, with the realised value and tolerance band.

Memory and interfaces

What a link or a memory interface actually delivers once the overhead is subtracted, rather than the number on the front of the datasheet.

MCU / SoC family selector →
An interview to a shortlist of families worth evaluating — and why every other one was ruled out.
Memory bandwidth + latency →
DDR, LPDDR, GDDR and HBM after refresh, turnaround and row misses — not the headline figure.
Bus bandwidth after overhead →
PCIe, CXL, Ethernet, USB, CAN — line rate minus line coding and protocol framing.

Reference and conversion

Lookups rather than calculations — the things you need mid-task and would otherwise search for, with the assumptions each conversion depends on stated rather than hidden.

Resistor colour + SMD code →
Both directions, 4/5/6 band plus 3-digit, 4-digit and EIA-96, with an E-series check.
Unit converter for engineers →
dBm to volts at a stated impedance, VSWR, FIT to PMHF, copper weight, AWG — and the SI units.

Not electronics at all

Tools that have nothing to do with circuit boards, kept here because they are genuinely useful and carry no advertising, no email capture and no tracking — which is more than can be said for most of what comes up when you search for them.

Mortgage calculator →
Amortisation and what extra payments save. No ads, no email, no lead capture.
Word finder (rack + blanks) →
Rack letters and blanks to every playable word, scored — and the leave it gives you.
Wordle solver →
Ranks the next guess by expected information gain, not just what is still possible.

Which one you want

The safety tools follow the order a real project meets them. You start with a hazard and need an integrity level: that is ASIL determination. You have an integrity level and need to know whether one part can reach it: that is the FIT and PMHF budget calculator. You have several parts and need the system answer, plus a sense of which one is spending your budget: that is the FMEDA rollup. And when the question is about process and effects rather than failure rates, FMEA action priority triages what to work on first.

The board FIT calculator is the bridge between the two halves of this page: it turns a bill of materials and a mission profile into the failure rate the safety tools consume.

On the board side, PDN target impedance answers the question that decides most decoupling arguments — how low does the impedance have to be, and how many capacitors does that take — and the decoupling impedance plot then shows you the anti-resonant peaks that the first answer is blind to. Via stub resonance settles whether a link needs backdrilling, and the buck converter calculator sizes a power stage without steering you to anyone's part number.

What these are for, and what they are not

Every one of them is a budgeting and sensitivity aid. They are built to give you the right order of magnitude quickly, and — more usefully — to show you which input your answer is actually sensitive to. That second thing is normally worth more than the number, because it tells you where to spend effort.

None of them is evidence. A calculator cannot produce an FMEDA, an FMEA, or PDN sign-off, and no assessor or certification body will accept one as a work product. Where a tool simplifies something that matters — anti-resonance in a capacitor bank, dependent failures in a safety analysis, the difference between our transparent FMEA precedence rule and the AIAG-VDA handbook table — each page says so plainly rather than leaving you to find out later.

They also deliberately avoid ground that is already well covered. There are good free impedance, trace-width and current-capacity calculators elsewhere, and we saw no reason to build worse copies. These fill the gaps we kept running into instead.

If the numbers are not landing

FMEDA and FMEA review, and signal and power integrity work, are two of our primary service lines. If a tool here is telling you something you do not like, the usual next step is a fixed-scope review — one to two weeks, ending in a written report you keep whether or not the work continues. The packages are listed with their scope and duration.

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New tools and notes, once a month at most

We add tools here fairly often and write up the things worth writing up — a stackup that behaved oddly, a standard that turned out to be obsolete, a calculator that was quietly wrong. Join and you get told when something new lands.

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