176 safety-instrumented IP blocks

On-chip serial and network controllers — CAN 2.0/FD/XL, FlexRay, automotive Ethernet, UART, SPI, I²C/I³C and storage links, each with ASIL safety instrumentation.

Root-of-trust and crypto — AES, SHA-2/3, HMAC, PKA, TRNG/DRBG, CRC, and secure on-board communication (SecOC).

The ASIL safety mechanisms and system glue — ECC memory, 2-of-3 TMR voters, lockstep safety wrappers, BIST, the fault-collection unit, and compute helpers.

AMBA↔TileLink protocol bridges, width/clock-domain converters, and crossbars that stitch a heterogeneous SoC together.

AMBA-5 CHI coherent fabric — home nodes (HN-F), request nodes, AXI↔CHI bridges, and the coherency crossbar, with ordering proven by formal.

The RISC-V platform layer — lockstep cores, boot ROM, caches, CLINT/CLIC/ACLINT, IOPMP, JTAG debug, mailbox, and the LPDDR5 controller.

Aerospace and defense buses — MIL-STD-1553, the ARINC 429/629/664/717/818/825 family, ECSS-CAN, and CCSDS space links.

Edge-inference building blocks — INT8 MAC clusters, tensor DMA, NPU stages, KV-cache compression engines, LM head, and an AI plausibility guard.

Motor and power control — FOC/BLDC commutation, high-resolution motor PWM, DC-DC control, quadrature encoders, and sigma-delta sensor front-ends.

Display and imaging pipelines — MIPI CSI-2/DSI, DisplayPort link, AVTP transport, and safety-monitored video encode.

UAV and robotics safety — DroneCAN, DShot ESC, RC receiver, Remote ID, teleop link guard, and a safety-chute trigger.

The housekeeping layer — timers/counters, watchdogs (incl. windowed), real-time clock, clock/reset generation, and GPIO.

Additional building blocks that don't fit a single family.

Integrated, pre-assembled safety subsystems delivered with a rolled-up FMEDA.